[Mesa-dev] [PATCH 4/4] i965/fs: Optimize (gl_FrontFacing ? x : -1.0) where x is ±0.0.

[Matt Turner]

The pattern

   gl_FrontFacing ? -0.0 : -1.0

appears in many shaders, but there's no significance of the 0.0's sign
since it the result of the expression is always used in an addition.

Getting the sign bit right would be an extra OR instruction and seems
unnecessary.

total instructions in shared programs: 5884883 -> 5883393 (-0.03%)
instructions in affected programs:     194415 -> 192925 (-0.77%)
GAINED:                                2
LOST:                                  0

(one of the GAINED programs had been lost in the previous commit)
---
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 31 ++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 1026af4..917d6fb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2770,6 +2770,37 @@ fs_visitor::try_opt_frontfacing_ternary(ir_if *ir)
       }
       emit(AND(dst, tmp, fs_reg(0xbf800000)));
       return true;
+   } else if (then_rhs->is_zero() && else_rhs->is_negative_one()) {
+      then_assign->lhs->accept(this);
+      fs_reg dst = this->result;
+      dst.type = BRW_REGISTER_TYPE_D;
+      fs_reg tmp = fs_reg(this, glsl_type::int_type);
+
+      if (brw->gen >= 6) {
+         /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
+         fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
+
+         /* For (gl_FrontFacing ? 0.0 : -1.0), emit:
+          *
+          *    asr(8) tmp<1>D    g0.0<0,1,0>W  15D
+          *    and(8) dst<1>D    tmp<1>D       0xbf800000D
+          */
+
+         emit(ASR(tmp, g0, fs_reg(15)));
+      } else {
+         /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
+         fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
+
+         /* For (gl_FrontFacing ? 0.0 : -1.0), emit:
+          *
+          *    asr(8) tmp<1>D    g1.6<0,1,0>D  31D
+          *    and(8) dst<1>D    tmp<1>D       0xbf800000D
+          */
+
+         emit(ASR(tmp, g1_6, fs_reg(31)));
+      }
+      emit(AND(dst, tmp, fs_reg(0xbf800000)));
+      return true;
    }
 
    return false;
-- 
2.0.4