[Mesa-dev] [PATCH v2 2/2] i965: Use the predicate enable bit for conditional rendering without stalling

Neil Roberts neil at linux.intel.com
Fri Jan 9 09:27:24 PST 2015


Daniel Vetter <daniel at ffwll.ch> writes:

> Oh, I guess my earlier mail was too late. One issue still is picking
> the numbers, since you seem to assume here that ver >= 2 means the
> stuff actually works. But like Ken said the cmd parser in upstream
> isn't really enabled yet.

The patch only enables the predicate enable bit if the ver >= 2 *and* it
can do register writes. The register write test already exists to check
whether we can do some transform feedback extensions and indirect
rendering. Therefore I think the patch is safe to land. It will
currently work on IvyBridge with master of Linus' kernel tree and
presumably it will magically start working on Haswell+ if we disable the
hardware validator there too. In the meantime I think it will safely
detect that the feature isn't available and fallback to the old blocking
path.

Considering that, would anyone be able to review the patch? It'd be a
shame to forget about this feature.

- Neil


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