[Mesa-dev] [PATCH 05/16] i965: Add backend_instruction::can_do_cmod().

[Kenneth Graunke]

On Monday, January 19, 2015 03:31:04 PM Matt Turner wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_shader.cpp | 45 ++++++++++++++++++++++++++++++++
>  src/mesa/drivers/dri/i965/brw_shader.h   |  1 +
>  2 files changed, 46 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index d76134b..cbdf976 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -790,6 +790,51 @@ backend_instruction::can_do_saturate() const
>  }
>  
>  bool
> +backend_instruction::can_do_cmod() const
> +{
> +   switch (opcode) {
> +   case BRW_OPCODE_ADD:
> +   case BRW_OPCODE_ADDC:
> +   case BRW_OPCODE_AND:
> +   case BRW_OPCODE_ASR:
> +   case BRW_OPCODE_AVG:
> +   case BRW_OPCODE_CMP:
> +   case BRW_OPCODE_CMPN:
> +   case BRW_OPCODE_DP2:
> +   case BRW_OPCODE_DP3:
> +   case BRW_OPCODE_DP4:
> +   case BRW_OPCODE_DPH:
> +   case BRW_OPCODE_F16TO32:
> +   case BRW_OPCODE_F32TO16:
> +   case BRW_OPCODE_FRC:
> +   case BRW_OPCODE_LINE:
> +   case BRW_OPCODE_LRP:
> +   case BRW_OPCODE_LZD:
> +   case BRW_OPCODE_MAC:
> +   case BRW_OPCODE_MACH:
> +   case BRW_OPCODE_MAD:
> +   case BRW_OPCODE_MOV:
> +   case BRW_OPCODE_MUL:
> +   case BRW_OPCODE_NOT:
> +   case BRW_OPCODE_OR:
> +   case BRW_OPCODE_PLN:
> +   case BRW_OPCODE_RNDD:
> +   case BRW_OPCODE_RNDE:
> +   case BRW_OPCODE_RNDU:
> +   case BRW_OPCODE_RNDZ:
> +   case BRW_OPCODE_SAD2:
> +   case BRW_OPCODE_SADA2:
> +   case BRW_OPCODE_SHL:
> +   case BRW_OPCODE_SHR:
> +   case BRW_OPCODE_SUBB:
> +   case BRW_OPCODE_XOR:
> +      return true;

I checked this function against the Gen4 and Gen8 docs, and I spied a few
missing opcodes:

- DIM (only exists on Haswell - I guess we don't have a #define yet)
- CSEL (only exists on Gen8+)
- SEL on Gen6+
- IF/WHILE on Sandybridge only

But, I suppose the conditional modifier behaves differently for SEL, CSEL, IF,
and WHILE, so it probably makes sense to omit them.  Maybe add a comment
explaining SEL's absence?

Patches 1-5 are:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

> +   default:
> +      return false;
> +   }
> +}
> +
> +bool
>  backend_instruction::reads_accumulator_implicitly() const
>  {
>     switch (opcode) {
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
> index 233e224..54d770e 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.h
> +++ b/src/mesa/drivers/dri/i965/brw_shader.h
> @@ -87,6 +87,7 @@ struct backend_instruction : public exec_node {
>     bool is_control_flow() const;
>     bool can_do_source_mods() const;
>     bool can_do_saturate() const;
> +   bool can_do_cmod() const;
>     bool reads_accumulator_implicitly() const;
>     bool writes_accumulator_implicitly(struct brw_context *brw) const;
>  
> 
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