[Mesa-dev] [PATCH] radeonsi: Enable VGPR spilling for all shader types v3

[Michel Dänzer]

On 20.01.2015 22:39, Marek Olšák wrote:
> The problem with CPDMA (DMA_DATA and WRITE_DATA) is that the ordering
> of flushes must be correct. First, partial flushes must be done, so
> that the shaders are idle.

That's only necessary when reusing a single BO for the shader code, not
when allocating a new BO when the relocations change, right?


> Then you can use CP DMA to update the binary. After that, ICACHE should
> be invalidated.

ICACHE has to be invalidated when writing with the CPU as well, right?


> The problem with mapping VRAM can be avoided by keeping a CPU copy of
> the binary from the beginning. We would only need a CPU copy of those
> shaders that use the scratch buffer. Then, you wouldn't have to read
> VRAM at all, which would make it even simpler.

Right, but CPU writes to the new BO in VRAM could cause stalls anyway.


Anyway, let's do it with the CPU first and maybe using CPDMA as an
optimization later.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer