[Mesa-dev] [PATCH 3/3] i965: Fix URB size for gen8

[Kenneth Graunke]

On Wednesday, January 21, 2015 08:17:36 PM ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Increase the device info .urb.size for BDW GT3 and CHV to match the
> default URB size for each.
> 
> Also add all missing platforms (BYT,BDW,CHV) to the comment describing
> the default URB size in gen7_urb.c.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_device_info.c | 4 ++--
>  src/mesa/drivers/dri/i965/gen7_urb.c        | 5 ++++-
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
> index bdef42b..d0b9e05 100644
> --- a/src/mesa/drivers/dri/i965/brw_device_info.c
> +++ b/src/mesa/drivers/dri/i965/brw_device_info.c
> @@ -226,7 +226,7 @@ static const struct brw_device_info brw_device_info_bdw_gt3 = {
>     GEN8_FEATURES, .gt = 3,
>     .max_wm_threads = 384,
>     .urb = {
> -      .size = 384,
> +      .size = 768,
>        .min_vs_entries = 64,
>        .max_vs_entries = 2560,
>        .max_gs_entries = 960,
> @@ -243,7 +243,7 @@ static const struct brw_device_info brw_device_info_chv = {
>     .max_gs_threads = 80,
>     .max_wm_threads = 128,
>     .urb = {
> -      .size = 128,
> +      .size = 192,
>        .min_vs_entries = 34,
>        .max_vs_entries = 640,
>        .max_gs_entries = 256,
> diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
> index 201f42e..f90d6e3 100644
> --- a/src/mesa/drivers/dri/i965/gen7_urb.c
> +++ b/src/mesa/drivers/dri/i965/gen7_urb.c
> @@ -50,9 +50,12 @@
>   * Currently we split the constant buffer space evenly among whatever stages
>   * are active.  This is probably not ideal, but simple.
>   *
> - * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
> + * Ivybridge GT1, Baytrail and Haswell GT1 have 128kB of URB space.
>   * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
>   * Haswell GT3 has 512kB of URB space.
> + * Broadwell GT1 and Cherryview have 192kB of URB space.
> + * Broadwell GT2 has 384kB of URB space.
> + * Broadwell GT3 has 768kB of URB space.
>   *
>   * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations",
>   * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
> 

Have you tested this?  I tried 768k on Broadwell GT3 a while back and got
no end of GPU hangs.  Which is odd, because it should be the correct value.

We really need to be programming the L3 to a known configuration and not
relying on default values...

--Ken
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