[Mesa-dev] [PATCH] i965: Add brw_state_reloc() for adding relocations to batch state objects
Kristian Høgsberg
krh at bitplanet.net
Tue Jan 27 21:08:53 PST 2015
We have intel_batchbuffer_emit_reloc(), which combines calculating and writing
out the right value to the batch buffer with emitting the relocation. It
determines the relocation offset from the current batch buffer position and
calculates the value to write in the batch buffer from the bo presumed offset
and the passed in delta. This commit introduces brw_state_reloc() and
brw_state_reloc64(), which provide similar convenience for batch state
relocations.
Signed-off-by: Kristian Høgsberg <krh at bitplanet.net>
---
src/mesa/drivers/dri/i965/brw_cc.c | 11 +---
src/mesa/drivers/dri/i965/brw_clip_state.c | 11 +---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 13 ++---
src/mesa/drivers/dri/i965/brw_sf_state.c | 20 +++----
src/mesa/drivers/dri/i965/brw_state.h | 10 ++++
src/mesa/drivers/dri/i965/brw_state_batch.c | 44 +++++++++++++++
src/mesa/drivers/dri/i965/brw_vs_state.c | 32 +++--------
src/mesa/drivers/dri/i965/brw_wm_state.c | 42 ++++----------
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 69 ++++++++---------------
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 13 +----
src/mesa/drivers/dri/i965/gen6_surface_state.c | 12 +---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 13 +----
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 52 ++++++-----------
src/mesa/drivers/dri/i965/gen8_surface_state.c | 59 +++++--------------
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 -
15 files changed, 153 insertions(+), 251 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 02f5a3a..388e6d0 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -227,17 +227,10 @@ static void upload_cc_unit(struct brw_context *brw)
cc->cc5.statistics_enable = 1;
/* BRW_NEW_CC_VP */
- cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 +
- brw->cc.vp_offset) >> 5; /* reloc */
+ brw_state_reloc(brw, &cc->cc4, brw->batch.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0, brw->cc.vp_offset);
brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
-
- /* Emit CC viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- (brw->cc.state_offset +
- offsetof(struct brw_cc_unit_state, cc4)),
- brw->batch.bo, brw->cc.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
}
const struct brw_tracked_state brw_cc_unit = {
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 09a2523..4bfa06f 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -131,15 +131,8 @@ brw_upload_clip_unit(struct brw_context *brw)
ctx->ViewportArray[0].Height == (float) fb->Height)
{
clip->clip5.guard_band_enable = 1;
- clip->clip6.clipper_viewport_state_ptr =
- (brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5;
-
- /* emit clip viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- (brw->clip.state_offset +
- offsetof(struct brw_clip_unit_state, clip6)),
- brw->batch.bo, brw->clip.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ brw_state_reloc(brw, &clip->clip6, brw->batch.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0, brw->clip.vp_offset);
}
/* _NEW_TRANSFORM */
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 0fe0853..298a09a 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -99,14 +99,11 @@ brw_emit_sampler_state(struct brw_context *brw,
SET_FIELD(mag_filter, BRW_SAMPLER_MAG_FILTER) |
SET_FIELD(min_filter, BRW_SAMPLER_MIN_FILTER);
- ss[2] = border_color_offset;
- if (brw->gen < 6) {
- ss[2] += brw->batch.bo->offset64; /* reloc */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- batch_offset_for_sampler_state + 8,
- brw->batch.bo, border_color_offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
- }
+ if (brw->gen < 6)
+ brw_state_reloc(brw, &ss[2], brw->batch.bo,
+ I915_GEM_DOMAIN_SAMPLER, 0, border_color_offset);
+ else
+ ss[2] = border_color_offset;
ss[3] = SET_FIELD(max_anisotropy, BRW_SAMPLER_MAX_ANISOTROPY) |
SET_FIELD(address_rounding, BRW_SAMPLER_ADDRESS_ROUNDING);
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 75d6451..227c99a 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -126,7 +126,6 @@ static void upload_sf_unit( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
struct brw_sf_unit_state *sf;
- drm_intel_bo *bo = brw->batch.bo;
int chipset_max_threads;
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
@@ -171,10 +170,6 @@ static void upload_sf_unit( struct brw_context *brw )
if (unlikely(INTEL_DEBUG & DEBUG_STATS))
sf->thread4.stats_enable = 1;
- /* BRW_NEW_SF_VP */
- sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
- brw->sf.vp_offset) >> 5; /* reloc */
-
sf->sf5.viewport_transform = 1;
/* _NEW_SCISSOR */
@@ -193,6 +188,13 @@ static void upload_sf_unit( struct brw_context *brw )
*/
sf->sf5.front_winding ^= render_to_fbo;
+ /* BRW_NEW_SF_VP */
+ brw_state_reloc(brw, &sf->sf5, brw->batch.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ (brw->sf.vp_offset |
+ sf->sf5.front_winding |
+ (sf->sf5.viewport_transform << 1)));
+
/* _NEW_POLYGON */
switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
case GL_FRONT:
@@ -283,14 +285,6 @@ static void upload_sf_unit( struct brw_context *brw )
* something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
*/
- /* Emit SF viewport relocation */
- drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
- offsetof(struct brw_sf_unit_state, sf5)),
- brw->batch.bo, (brw->sf.vp_offset |
- sf->sf5.front_winding |
- (sf->sf5.viewport_transform << 1)),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
-
brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index f195407..1b7eea2 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -202,6 +202,16 @@ void *brw_state_batch(struct brw_context *brw,
int alignment,
uint32_t *out_offset);
+void brw_state_reloc(struct brw_context *brw,
+ void *p, drm_intel_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta);
+
+void brw_state_reloc64(struct brw_context *brw,
+ void *p, drm_intel_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta);
+
/* brw_wm_surface_state.c */
void gen4_init_vtable_surface_functions(struct brw_context *brw);
uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 45dca69..0ea3d96 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -29,6 +29,7 @@
* Keith Whitwell <keithw at vmware.com>
*/
+#include "intel_bufmgr.h"
#include "brw_state.h"
#include "intel_batchbuffer.h"
#include "main/imports.h"
@@ -145,3 +146,46 @@ brw_state_batch(struct brw_context *brw,
*out_offset = offset;
return batch->map + (offset>>2);
}
+
+static inline bool
+in_state_batch(struct brw_context *brw, void *p)
+{
+ return (void *) brw->batch.map + brw->batch.state_batch_offset <= p &&
+ p < (void *) brw->batch.map + brw->batch.bo->size;
+}
+
+void
+brw_state_reloc(struct brw_context *brw,
+ void *p, drm_intel_bo *target,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta)
+{
+ assert(in_state_batch(brw, p));
+
+ if (target) {
+ drm_intel_bo_emit_reloc(brw->batch.bo, p - (void *) brw->batch.map,
+ target, delta, read_domains, write_domain);
+
+ *((uint32_t *) p) = target->offset64 + delta;
+ } else {
+ *((uint32_t *) p) = delta;
+ }
+}
+
+void
+brw_state_reloc64(struct brw_context *brw,
+ void *p, drm_intel_bo *target,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta)
+{
+ assert(in_state_batch(brw, p));
+
+ if (target) {
+ drm_intel_bo_emit_reloc(brw->batch.bo, p - (void *) brw->batch.map,
+ target, delta, read_domains, write_domain);
+
+ *((uint64_t *) p) = target->offset64 + delta;
+ } else {
+ *((uint64_t *) p) = delta;
+ }
+}
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 17bdbb9..8f6bd27 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -80,10 +80,9 @@ brw_upload_vs_unit(struct brw_context *brw)
brw->vs.prog_data->base.base.binding_table.size_bytes / 4;
if (brw->vs.prog_data->base.base.total_scratch != 0) {
- vs->thread2.scratch_space_base_pointer =
- stage_state->scratch_bo->offset64 >> 10; /* reloc */
- vs->thread2.per_thread_scratch_space =
- ffs(brw->vs.prog_data->base.base.total_scratch) - 11;
+ brw_state_reloc(brw, &vs->thread2, stage_state->scratch_bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ ffs(brw->vs.prog_data->base.base.total_scratch) - 11);
} else {
vs->thread2.scratch_space_base_pointer = 0;
vs->thread2.per_thread_scratch_space = 0;
@@ -153,29 +152,12 @@ brw_upload_vs_unit(struct brw_context *brw)
*/
vs->vs6.vs_enable = 1;
- /* Set the sampler state pointer, and its reloc
- */
+ /* Set the sampler state pointer, and its reloc */
if (stage_state->sampler_count) {
/* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
- vs->vs5.sampler_state_pointer =
- (brw->batch.bo->offset64 + stage_state->sampler_offset) >> 5;
- drm_intel_bo_emit_reloc(brw->batch.bo,
- stage_state->state_offset +
- offsetof(struct brw_vs_unit_state, vs5),
- brw->batch.bo,
- (stage_state->sampler_offset |
- vs->vs5.sampler_count),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
- }
-
- /* Emit scratch space relocation */
- if (brw->vs.prog_data->base.base.total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- stage_state->state_offset +
- offsetof(struct brw_vs_unit_state, thread2),
- stage_state->scratch_bo,
- vs->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ brw_state_reloc(brw, &vs->vs5, brw->batch.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ (stage_state->sampler_offset | vs->vs5.sampler_count));
}
brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 0dee1f8..25aff64 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -123,10 +123,9 @@ brw_upload_wm_unit(struct brw_context *brw)
prog_data->base.binding_table.size_bytes / 4;
if (prog_data->base.total_scratch != 0) {
- wm->thread2.scratch_space_base_pointer =
- brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
- wm->thread2.per_thread_scratch_space =
- ffs(prog_data->base.total_scratch) - 11;
+ brw_state_reloc(brw, &wm->thread2, brw->wm.base.scratch_bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ ffs(prog_data->base.total_scratch) - 11);
} else {
wm->thread2.scratch_space_base_pointer = 0;
wm->thread2.per_thread_scratch_space = 0;
@@ -142,6 +141,10 @@ brw_upload_wm_unit(struct brw_context *brw)
/* BRW_NEW_CURBE_OFFSETS */
wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
+ /* BRW_NEW_STATS_WM */
+ if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
+ wm->wm4.stats_enable = 1;
+
if (brw->gen == 5)
wm->wm4.sampler_count = 0; /* hardware requirement */
else {
@@ -150,8 +153,10 @@ brw_upload_wm_unit(struct brw_context *brw)
if (brw->wm.base.sampler_count) {
/* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
- wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
- brw->wm.base.sampler_offset) >> 5;
+ brw_state_reloc(brw, &wm->wm4, brw->batch.bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ (brw->wm.base.sampler_offset |
+ wm->wm4.stats_enable | (wm->wm4.sampler_count << 2)));
} else {
wm->wm4.sampler_state_pointer = 0;
}
@@ -212,31 +217,6 @@ brw_upload_wm_unit(struct brw_context *brw)
/* _NEW_LINE */
wm->wm5.line_stipple = ctx->Line.StippleFlag;
- /* BRW_NEW_STATS_WM */
- if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
- wm->wm4.stats_enable = 1;
-
- /* Emit scratch space relocation */
- if (prog_data->base.total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.state_offset +
- offsetof(struct brw_wm_unit_state, thread2),
- brw->wm.base.scratch_bo,
- wm->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- }
-
- /* Emit sampler state relocation */
- if (brw->wm.base.sampler_count != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.state_offset +
- offsetof(struct brw_wm_unit_state, wm4),
- brw->batch.bo, (brw->wm.base.sampler_offset |
- wm->wm4.stats_enable |
- (wm->wm4.sampler_count << 2)),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
- }
-
brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index bf7936c..b7bb51a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -231,22 +231,19 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
(brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
- surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
- surf[2] = (buffer_size & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
- ((buffer_size >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
- surf[3] = ((buffer_size >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
- (pitch - 1) << BRW_SURFACE_PITCH_SHIFT;
/* Emit relocation to surface contents. The 965 PRM, Volume 4, section
* 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
* physical cache. It is mapped in hardware to the sampler cache."
*/
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
- bo, buffer_offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- }
+ brw_state_reloc(brw, &surf[1], bo,
+ I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0), buffer_offset);
+
+ surf[2] = (buffer_size & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
+ ((buffer_size >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
+ surf[3] = ((buffer_size >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
+ (pitch - 1) << BRW_SURFACE_PITCH_SHIFT;
}
void
@@ -342,7 +339,9 @@ brw_update_texture_surface(struct gl_context *ctx,
BRW_SURFACE_CUBEFACE_ENABLES |
tex_format << BRW_SURFACE_FORMAT_SHIFT);
- surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
+ /* Emit relocation to surface contents */
+ brw_state_reloc(brw, &surf[1], mt->bo,
+ I915_GEM_DOMAIN_SAMPLER, 0, mt->offset);
surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
(mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -356,13 +355,6 @@ brw_update_texture_surface(struct gl_context *ctx,
SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_SAMPLER, 0);
}
/**
@@ -455,19 +447,18 @@ brw_update_sol_surface(struct brw_context *brw,
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = bo->offset64 + offset_bytes; /* reloc */
+
+ /* Emit relocation to surface contents. */
+ brw_state_reloc(brw, &surf[1], bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ offset_bytes);
+
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
surf[4] = 0;
surf[5] = 0;
-
- /* Emit relocation to surface contents. */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4,
- bo, offset_bytes,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
/* Creates a new WM constant buffer reflecting the current fragment program's
@@ -581,7 +572,10 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
- surf[1] = bo ? bo->offset64 : 0;
+
+ brw_state_reloc(brw, &surf[1], bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+
surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -594,13 +588,6 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
surf[4] = multisampling_state;
surf[5] = 0;
-
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
- bo, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- }
}
/**
@@ -657,10 +644,11 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
format << BRW_SURFACE_FORMAT_SHIFT);
- /* reloc */
assert(mt->offset % mt->cpp == 0);
- surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
- mt->bo->offset64 + mt->offset);
+ brw_state_reloc(brw, &surf[1], mt->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
+ mt->offset);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -701,13 +689,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
}
}
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
}
/**
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d4aa955..72758f6 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -379,9 +379,9 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
BRW_SURFACE_CUBEFACE_ENABLES |
surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
- /* reloc */
- surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
- mt->bo->offset64);
+ brw_state_reloc(brw, &surf[1], mt->bo,
+ read_domains, write_domain,
+ surface->compute_tile_offsets(&tile_x, &tile_y));
surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
(width - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -409,13 +409,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
(surface->mt->align_h == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- wm_surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- read_domains, write_domain);
-
return wm_surf_offset;
}
diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index 080e0f3..b2d0c73 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -96,9 +96,10 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
surf[0] = SET_FIELD(surftype, BRW_SURFACE_TYPE) |
SET_FIELD(format, BRW_SURFACE_FORMAT);
- /* reloc */
assert(mt->offset % mt->cpp == 0);
- surf[1] = mt->bo->offset64 + mt->offset;
+ brw_state_reloc(brw, &surf[1], mt->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ mt->offset);
/* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
* (Surface Arrays For all surfaces other than separate stencil buffer):
@@ -129,13 +130,6 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
SET_FIELD(depth - 1, BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT);
surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
}
void
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 206a6ff..346f001 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -174,9 +174,9 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
else
surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
- /* reloc */
- surf[1] =
- surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
+ brw_state_reloc(brw, &surf[1], mt->bo,
+ read_domains, write_domain,
+ surface->compute_tile_offsets(&tile_x, &tile_y));
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
@@ -210,13 +210,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
}
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- wm_surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- read_domains, write_domain);
-
gen7_check_surface_setup(surf, is_render_target);
return wm_surf_offset;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 68f81d9..7b31b62 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -116,18 +116,12 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
* the necessary address translation.
*/
assert ((mcs_mt->bo->offset64 & 0xfff) == 0);
-
- surf[6] = GEN7_SURFACE_MCS_ENABLE |
- SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
- mcs_mt->bo->offset64;
-
- drm_intel_bo_emit_reloc(brw->batch.bo,
- surf_offset + 6 * 4,
- mcs_mt->bo,
- surf[6] & 0xfff,
- is_render_target ? I915_GEM_DOMAIN_RENDER
- : I915_GEM_DOMAIN_SAMPLER,
- is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
+ brw_state_reloc(brw, &surf[6], mcs_mt->bo,
+ is_render_target ? I915_GEM_DOMAIN_RENDER
+ : I915_GEM_DOMAIN_SAMPLER,
+ is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+ GEN7_SURFACE_MCS_ENABLE |
+ SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH));
}
@@ -235,7 +229,11 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
+
+ brw_state_reloc(brw, &surf[1], bo,
+ I915_GEM_DOMAIN_SAMPLER, (rw ? I915_GEM_DOMAIN_SAMPLER : 0),
+ buffer_offset);
+
surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
@@ -250,13 +248,6 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
}
- /* Emit relocation to surface contents */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- }
-
gen7_check_surface_setup(surf, false /* is_render_target */);
}
@@ -314,7 +305,8 @@ gen7_update_texture_surface(struct gl_context *ctx,
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
- surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
+ brw_state_reloc(brw, &surf[1], mt->bo,
+ I915_GEM_DOMAIN_SAMPLER, 0, mt->offset);
surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
@@ -360,13 +352,6 @@ gen7_update_texture_surface(struct gl_context *ctx,
mt->mcs_mt, false /* is RT */);
}
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_SAMPLER, 0);
-
gen7_check_surface_setup(surf, false /* is_render_target */);
}
@@ -518,7 +503,9 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
}
assert(mt->offset % mt->cpp == 0);
- surf[1] = mt->bo->offset64 + mt->offset;
+ brw_state_reloc(brw, &surf[1], mt->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ mt->offset);
assert(brw->has_surface_tile_offset);
@@ -549,13 +536,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
-
gen7_check_surface_setup(surf, true /* is_render_target */);
}
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 45c35db..fe3ad40 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -134,15 +134,10 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
- /* reloc */
- *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
-
- /* Emit relocation to surface contents. */
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- rw ? I915_GEM_DOMAIN_SAMPLER : 0);
- }
+
+ brw_state_reloc64(brw, &surf[8], bo,
+ I915_GEM_DOMAIN_SAMPLER, rw ? I915_GEM_DOMAIN_SAMPLER : 0,
+ buffer_offset);
}
static void
@@ -253,25 +248,13 @@ gen8_update_texture_surface(struct gl_context *ctx,
SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
- *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
+ brw_state_reloc64(brw, &surf[8], mt->bo,
+ I915_GEM_DOMAIN_SAMPLER, 0, mt->offset);
- if (aux_mt) {
- *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
- drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
- aux_mt->bo, 0,
- I915_GEM_DOMAIN_SAMPLER, 0);
- } else {
- surf[10] = 0;
- surf[11] = 0;
- }
- surf[12] = 0;
+ brw_state_reloc64(brw, &surf[10], aux_mt->bo,
+ I915_GEM_DOMAIN_SAMPLER, 0, 0);
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 8 * 4,
- mt->bo,
- mt->offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ surf[12] = 0;
}
static void
@@ -433,26 +416,14 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
assert(mt->offset % mt->cpp == 0);
- *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
+ brw_state_reloc64(brw, &surf[8], mt->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ mt->offset);
- if (aux_mt) {
- *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 10 * 4,
- aux_mt->bo, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- } else {
- surf[10] = 0;
- surf[11] = 0;
- }
- surf[12] = 0;
+ brw_state_reloc64(brw, &surf[10], aux_mt->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 8 * 4,
- mt->bo,
- 0,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ surf[12] = 0;
}
void
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 654dcdb..3461275 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -341,9 +341,6 @@ _intel_batchbuffer_flush(struct brw_context *brw,
return ret;
}
-
-/* This is the only way buffers get added to the validate list.
- */
bool
intel_batchbuffer_emit_reloc(struct brw_context *brw,
drm_intel_bo *buffer,
--
2.2.1
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