[Mesa-dev] [PATCH] i965/chv|skl: Apply sampler bypass w/a

[Ben Widawsky]

Certain compressed formats require this setting. The docs don't go into much
detail as to why it's needed exactly.

This fixes 0 piglit failures with a GBM gpu piglit run.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---

I had this one sitting around for almost 2 months. I'm not sure why I didn't
send it out sooner. It seems like it's needed.

---
 src/mesa/drivers/dri/i965/brw_defines.h        |  1 +
 src/mesa/drivers/dri/i965/gen8_surface_state.c | 26 ++++++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 66b9abc..f55fd49 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -276,6 +276,7 @@
 #define GEN8_SURFACE_TILING_W                       (1 << 12)
 #define GEN8_SURFACE_TILING_X                       (2 << 12)
 #define GEN8_SURFACE_TILING_Y                       (3 << 12)
+#define GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE      (1 << 9)
 #define BRW_SURFACE_RC_READ_WRITE	(1 << 8)
 #define BRW_SURFACE_MIPLAYOUT_SHIFT	10
 #define BRW_SURFACE_MIPMAPLAYOUT_BELOW   0
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index ca5ed17..a245379 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -264,6 +264,19 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
    }
 
+   if (brw->is_cherryview || brw->gen >= 9) {
+      /* "This bit must be set for the following surface types: BC2_UNORM
+       * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM"
+       */
+      switch (format) {
+      case BRW_SURFACEFORMAT_BC2_UNORM:
+      case BRW_SURFACEFORMAT_BC3_UNORM:
+      case BRW_SURFACEFORMAT_BC5_SNORM:
+      case BRW_SURFACEFORMAT_BC7_UNORM:
+         surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE;
+      }
+   }
+
    if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 
@@ -491,6 +504,19 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
              horizontal_alignment(brw, mt, surf_type) |
              surface_tiling_mode(tiling);
 
+   if (brw->is_cherryview || brw->gen >= 9) {
+      /* "This bit must be set for the following surface types: BC2_UNORM
+       * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM"
+       */
+      switch (format) {
+      case BRW_SURFACEFORMAT_BC2_UNORM:
+      case BRW_SURFACEFORMAT_BC3_UNORM:
+      case BRW_SURFACEFORMAT_BC5_SNORM:
+      case BRW_SURFACEFORMAT_BC7_UNORM:
+         surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE;
+      }
+   }
+
    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 
    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
-- 
2.4.5