[Mesa-dev] [PATCH] i965/skl: Emit new 3DSTATE_VF_COMPONENT_PACKING
Ben Widawsky
benjamin.widawsky at intel.com
Wed Jul 1 16:06:54 PDT 2015
We don't yet have a use for this state, but initializing it to known values is
always considered wise. In general NULL state can probably go in the misc state
upload, I only put it here because I assume it might be useful at some point.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
I've had this patch sitting around for almost 3 months now. I believe we like to
initialize new fields as a general rule of thumb.
---
src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 29 ++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 66b9abc..444d974 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1713,6 +1713,8 @@ enum brw_message_target {
#define _3DSTATE_VF_TOPOLOGY 0x784b /* GEN8+ */
+#define _3DSTATE_VF_COMPONENT_PACKING 0x7855 /* GEN9+ */
+
#define _3DSTATE_WM_CHROMAKEY 0x784c /* GEN8+ */
#define _3DSTATE_URB_VS 0x7830 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 1af90ec..f6e7fc8 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -35,6 +35,33 @@
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
+/**
+ * Emits a null component packing state.
+ *
+ * Paraphrasing the docs: "This command is used to specify which 32-bit
+ * components are "enabled" to be stored in the URB, and which are "disabled".
+ * Disabling all four components for a given Vertex Element will result in no
+ * data stored for that element. Note that any insertion of SGVs
+ * (3DSTATE_VF_SGVS) is performed before the packing operation."
+ *
+ * FINISHME: "Component packing is probably only useful for SIMD8 VS thread
+ * execution." When enabled, the correct bit must be set in 3DSTATE_VF.
+ */
+static void
+gen9_emit_component_packing(struct brw_context *brw)
+{
+ if (brw->gen < 9)
+ return;
+
+ BEGIN_BATCH(5);
+ OUT_BATCH(_3DSTATE_VF_COMPONENT_PACKING << 16 | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
+
static void
gen8_emit_vertices(struct brw_context *brw)
{
@@ -44,6 +71,8 @@ gen8_emit_vertices(struct brw_context *brw)
brw_prepare_vertices(brw);
brw_prepare_shader_draw_parameters(brw);
+ gen9_emit_component_packing(brw);
+
if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid) {
unsigned vue = brw->vb.nr_enabled;
--
2.4.4
More information about the mesa-dev
mailing list