[Mesa-dev] [PATCH 08/18] i965: Coalesce relocation read/write domains to a single integer
Chris Wilson
chris at chris-wilson.co.uk
Mon Jul 6 03:33:13 PDT 2015
There are only a handful of distinct cache domains (less than 16), and
internally the kernel simply doesn't care other than whether the object
is a render target. We can therefore trim a parameter by coalescing the
relocation domains to a single unsigned bitfield without loss of
generality.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.c | 11 ++++----
src/mesa/drivers/dri/i965/brw_batch.h | 19 +++++++------
src/mesa/drivers/dri/i965/brw_cc.c | 2 +-
src/mesa/drivers/dri/i965/brw_clip_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_conditional_render.c | 6 ++--
src/mesa/drivers/dri/i965/brw_context.c | 14 +++++-----
src/mesa/drivers/dri/i965/brw_context.h | 6 ++--
src/mesa/drivers/dri/i965/brw_cs.cpp | 4 +--
src/mesa/drivers/dri/i965/brw_curbe.c | 2 +-
src/mesa/drivers/dri/i965/brw_draw.c | 12 ++++----
src/mesa/drivers/dri/i965/brw_draw_upload.c | 12 +++-----
src/mesa/drivers/dri/i965/brw_misc_state.c | 31 ++++++++++-----------
.../drivers/dri/i965/brw_performance_monitor.c | 10 +++----
src/mesa/drivers/dri/i965/brw_pipe_control.c | 8 ++----
src/mesa/drivers/dri/i965/brw_sampler_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_sf_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_vs_state.c | 5 ++--
src/mesa/drivers/dri/i965/brw_wm_state.c | 4 +--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 31 ++++++++-------------
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 26 ++++++++----------
src/mesa/drivers/dri/i965/gen6_depth_state.c | 12 ++------
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_queryobj.c | 8 +++---
src/mesa/drivers/dri/i965/gen6_surface_state.c | 3 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 13 ++++-----
src/mesa/drivers/dri/i965/gen7_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 13 ++-------
src/mesa/drivers/dri/i965/gen7_sol_state.c | 8 +++---
src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 +--
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 19 +++++++------
src/mesa/drivers/dri/i965/gen8_depth_state.c | 9 ++----
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 6 ++--
src/mesa/drivers/dri/i965/gen8_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_misc_state.c | 8 ++++--
src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_sol_state.c | 4 +--
src/mesa/drivers/dri/i965/gen8_surface_state.c | 14 ++++------
src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/intel_blit.c | 32 ++++++----------------
src/mesa/drivers/dri/i965/intel_extensions.c | 4 +--
43 files changed, 161 insertions(+), 221 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.c b/src/mesa/drivers/dri/i965/brw_batch.c
index 24e96c6..bfff9fe 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_batch.c
@@ -802,8 +802,7 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
uint32_t batch_offset,
struct brw_bo *target_bo,
uint64_t target_offset,
- unsigned read_domains,
- unsigned write_domain)
+ unsigned domains)
{
assert(target_bo->refcnt);
if (unlikely(target_bo->batch != batch)) {
@@ -854,8 +853,8 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
batch->reloc[n].delta = target_offset;
batch->reloc[n].target_handle = target_bo->target_handle;
batch->reloc[n].presumed_offset = target_bo->offset;
- batch->reloc[n].read_domains = read_domains;
- batch->reloc[n].write_domain = write_domain;
+ batch->reloc[n].read_domains = domains & 0xffff;
+ batch->reloc[n].write_domain = domains >> 16;
/* If we haven't added the batch to the execobject array yet, we
* will have to process all the relocations pointing to the
@@ -868,7 +867,7 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
}
}
- if (write_domain && !target_bo->dirty) {
+ if (domains >> 16 && !target_bo->dirty) {
assert(target_bo != batch->bo);
target_bo->write.rq = batch->next_request;
list_move(&target_bo->write.link, &batch->next_request->write);
@@ -877,7 +876,7 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
target_bo->domain = DOMAIN_GPU;
if (has_lut(batch)) {
target_bo->exec->flags |= EXEC_OBJECT_WRITE;
- if (write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
+ if ((domains >> 16) == I915_GEM_DOMAIN_INSTRUCTION &&
batch->needs_pipecontrol_ggtt_wa)
target_bo->exec->flags |= EXEC_OBJECT_NEEDS_GTT;
}
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 0b5468b..5b56e82 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -157,25 +157,26 @@ void brw_batch_clear_dirty(struct brw_batch *batch);
/** Add a relocation entry to the current batch
* XXX worth specialising 32bit variant?
*/
+#define __BRW_DOMAINS(read, write) (((write) << 16) | (read))
+#define BRW_DOMAINS(read, write) \
+ __BRW_DOMAINS(I915_GEM_DOMAIN_##read, write ? I915_GEM_DOMAIN_##read : 0)
uint64_t __brw_batch_reloc(struct brw_batch *batch,
uint32_t batch_offset,
struct brw_bo *target_bo,
uint64_t target_offset,
- unsigned read_domains,
- unsigned write_domain);
+ unsigned domains);
must_check static inline uint64_t brw_batch_reloc(struct brw_batch *batch,
uint32_t batch_offset,
struct brw_bo *target_bo,
uint64_t target_offset,
- unsigned read_domains,
- unsigned write_domain)
+ unsigned domains)
{
if (target_bo == NULL)
return target_offset;
return __brw_batch_reloc(batch, batch_offset,
target_bo, target_offset,
- read_domains, write_domain);
+ domains);
}
int brw_batch_get_reset_stats(struct brw_batch *batch,
@@ -365,13 +366,13 @@ static inline void brw_batch_emit64(struct brw_batch *batch, uint64_t qw)
#define BEGIN_BATCH_BLT(n) __brw_batch_check(&brw->batch, n, BLT_RING)
#define OUT_BATCH(dw) brw_batch_emit(&brw->batch, dw)
#define OUT_BATCH_F(f) brw_batch_emit(&brw->batch, float_as_int(f))
-#define OUT_RELOC(bo, read_domains, write_domain, delta) \
+#define OUT_RELOC(bo, domains, delta) \
OUT_BATCH(brw_batch_reloc(&brw->batch, brw->batch.emit.nbatch*4, \
- bo, delta, read_domains, write_domain))
+ bo, delta, domains))
#define OUT_BATCH64(qw) brw_batch_emit64(&brw->batch, qw)
-#define OUT_RELOC64(bo, read_domains, write_domain, delta) \
+#define OUT_RELOC64(bo, domains, delta) \
OUT_BATCH64(brw_batch_reloc(&brw->batch, brw->batch.emit.nbatch*4,\
- bo, delta, read_domains, write_domain))
+ bo, delta, domains))
#define ADVANCE_BATCH()
#endif /* BRW_BATCH_H */
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 4f62b29..ab5cd16 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -231,7 +231,7 @@ static void upload_cc_unit(struct brw_context *brw)
(brw->cc.state_offset +
offsetof(struct brw_cc_unit_state, cc4)),
brw->batch.bo, brw->cc.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
+ BRW_DOMAINS(INSTRUCTION, false)) >> 5;
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 8307ecd..faa9532 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -140,7 +140,7 @@ brw_upload_clip_unit(struct brw_context *brw)
(brw->clip.state_offset +
offsetof(struct brw_clip_unit_state, clip6)),
brw->batch.bo, brw->clip.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
+ BRW_DOMAINS(INSTRUCTION, false)) >> 5;
}
/* _NEW_TRANSFORM */
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index ffd10a6..8bc63fc 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -59,14 +59,12 @@ set_predicate_for_result(struct brw_context *brw,
brw_load_register_mem64(brw,
MI_PREDICATE_SRC0,
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
+ BRW_DOMAINS(INSTRUCTION, false),
0 /* offset */);
brw_load_register_mem64(brw,
MI_PREDICATE_SRC1,
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
+ BRW_DOMAINS(INSTRUCTION, false),
8 /* offset */);
if (inverted)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index a8ed0b8..670cfb3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1556,7 +1556,7 @@ static void
load_sized_register_mem(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset,
int size)
{
@@ -1570,7 +1570,7 @@ load_sized_register_mem(struct brw_context *brw,
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC64(bo, domains, offset + i * 4);
}
ADVANCE_BATCH();
} else {
@@ -1578,7 +1578,7 @@ load_sized_register_mem(struct brw_context *brw,
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC(bo, domains, offset + i * 4);
}
ADVANCE_BATCH();
}
@@ -1588,18 +1588,18 @@ void
brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 1);
+ load_sized_register_mem(brw, reg, bo, domains, offset, 1);
}
void
brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2);
+ load_sized_register_mem(brw, reg, bo, domains, offset, 2);
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index e4fded3..63f4f87 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1565,12 +1565,12 @@ bool brw_check_conditional_render(struct brw_context *brw);
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset);
/*======================================================================
@@ -1857,7 +1857,7 @@ brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
return brw_batch_reloc(&brw->batch, state_offset,
brw->cache.bo, prog_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ BRW_DOMAINS(INSTRUCTION, 0));
}
bool brw_do_cubemap_normalize(struct exec_list *instructions);
diff --git a/src/mesa/drivers/dri/i965/brw_cs.cpp b/src/mesa/drivers/dri/i965/brw_cs.cpp
index ee1f481..b0425b4 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_cs.cpp
@@ -321,11 +321,11 @@ brw_upload_cs_state(struct brw_context *brw)
if (prog_data->total_scratch) {
if (brw->gen >= 8)
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(prog_data->total_scratch) - 11);
else
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(prog_data->total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 29b75bc..2075cde 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -299,7 +299,7 @@ emit:
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
OUT_RELOC(brw->curbe.curbe_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BRW_DOMAINS(INSTRUCTION, false),
(brw->curbe.total_size - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 1e967da..33e0d82 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -262,25 +262,25 @@ static void brw_emit_prim(struct brw_context *brw,
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 0);
brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 4);
brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 8);
if (prim->indexed) {
brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 12);
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 16);
} else {
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 12);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index bc2e8fa..c708bb1 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -634,9 +634,9 @@ emit_vertex_buffer_state(struct brw_context *brw,
"VBO stride %d too large, bad rendering may occur\n",
stride);
OUT_BATCH(dw0 | (stride << BRW_VB0_PITCH_SHIFT));
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, bo_offset);
+ OUT_RELOC(bo, BRW_DOMAINS(VERTEX, false), bo_offset);
if (brw->gen >= 5) {
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, bo_ending_address);
+ OUT_RELOC(bo, BRW_DOMAINS(VERTEX, false), bo_ending_address);
} else {
OUT_BATCH(0);
}
@@ -951,12 +951,8 @@ static void brw_emit_index_buffer(struct brw_context *brw)
cut_index_setting |
brw_get_index_type(index_buffer->type) |
1);
- OUT_RELOC(brw->ib.bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- 0);
- OUT_RELOC(brw->ib.bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- brw->ib.bo->size - 1);
+ OUT_RELOC(brw->ib.bo, BRW_DOMAINS(VERTEX, false), 0);
+ OUT_RELOC(brw->ib.bo, BRW_DOMAINS(VERTEX, false), brw->ib.bo->size - 1);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 5dd45da..b24078c 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -84,20 +84,20 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->vs.base.state_offset);
if (brw->ff_gs.prog_active)
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->ff_gs.state_offset | 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->clip.state_offset | 1);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->sf.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->wm.base.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->cc.state_offset);
ADVANCE_BATCH();
@@ -604,7 +604,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
if (depth_mt) {
OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
depth_offset);
} else {
OUT_BATCH(0);
@@ -640,7 +640,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_mt->pitch - 1);
OUT_RELOC(hiz_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
brw->depthstencil.hiz_offset);
ADVANCE_BATCH();
} else {
@@ -662,7 +662,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
*/
OUT_BATCH(2 * stencil_mt->pitch - 1);
OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
brw->depthstencil.stencil_offset);
ADVANCE_BATCH();
} else {
@@ -953,7 +953,7 @@ static void upload_state_base_address( struct brw_context *brw )
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(SAMPLER, false), 1);
/* Dynamic state base address:
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
@@ -964,11 +964,10 @@ static void upload_state_base_address( struct brw_context *brw )
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
- OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
- I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false), 1);
OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->cache.bo, BRW_DOMAINS(INSTRUCTION, false),
1); /* Instruction base address: shader kernels (incl. SIP) */
OUT_BATCH(1); /* General state upper bound */
@@ -985,10 +984,10 @@ static void upload_state_base_address( struct brw_context *brw )
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(SAMPLER, false),
1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->cache.bo, BRW_DOMAINS(INSTRUCTION, false),
1); /* Instruction base address */
OUT_BATCH(0xfffff001); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
@@ -998,7 +997,7 @@ static void upload_state_base_address( struct brw_context *brw )
BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(SAMPLER, false),
1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
index fd94348..06a9169 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
@@ -725,28 +725,26 @@ emit_mi_report_perf_count(struct brw_context *brw,
*/
BEGIN_BATCH(6);
OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | GEN5_MI_COUNTER_SET_0);
- OUT_RELOC(bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
offset_in_bytes);
OUT_BATCH(report_id);
OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | GEN5_MI_COUNTER_SET_1);
- OUT_RELOC(bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
offset_in_bytes + 64);
OUT_BATCH(report_id);
ADVANCE_BATCH();
} else if (brw->gen == 6) {
BEGIN_BATCH(3);
OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
offset_in_bytes | MI_COUNTER_ADDRESS_GTT);
OUT_BATCH(report_id);
ADVANCE_BATCH();
} else if (brw->gen == 7) {
BEGIN_BATCH(3);
OUT_BATCH(GEN6_MI_REPORT_PERF_COUNT);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
offset_in_bytes);
OUT_BATCH(report_id);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index c64fbb1..344af87 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -144,8 +144,7 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
OUT_BATCH(imm_lower);
OUT_BATCH(imm_upper);
ADVANCE_BATCH();
@@ -160,15 +159,14 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(flags);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- gen6_gtt | offset);
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), gen6_gtt | offset);
OUT_BATCH(imm_lower);
OUT_BATCH(imm_upper);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
OUT_BATCH(imm_lower);
OUT_BATCH(imm_upper);
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index a56356b..8ef74ab 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -102,7 +102,7 @@ brw_emit_sampler_state(struct brw_context *brw,
ss[2] = brw_batch_reloc(&brw->batch,
batch_offset_for_sampler_state + 8,
brw->batch.bo, border_color_offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ BRW_DOMAINS(SAMPLER, false));
} else
ss[2] = border_color_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 076166b..6e60fc3 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -201,7 +201,7 @@ static void upload_sf_unit( struct brw_context *brw )
(brw->sf.state_offset + offsetof(struct brw_sf_unit_state, sf5)),
brw->batch.bo,
brw->sf.vp_offset | sf->dw5,
- I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
+ BRW_DOMAINS(INSTRUCTION, false)) >> 5;
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 59d8c8c..7ea99ae 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -88,8 +88,7 @@ brw_upload_vs_unit(struct brw_context *brw)
stage_state->state_offset + offsetof(struct brw_vs_unit_state, thread2),
stage_state->scratch_bo,
vs->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER) >> 10;
+ BRW_DOMAINS(RENDER, true)) >> 10;
} else {
vs->thread2.scratch_space_base_pointer = 0;
vs->thread2.per_thread_scratch_space = 0;
@@ -168,7 +167,7 @@ brw_upload_vs_unit(struct brw_context *brw)
stage_state->state_offset + offsetof(struct brw_vs_unit_state, vs5),
brw->batch.bo,
(stage_state->sampler_offset | vs->vs5.sampler_count),
- I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
+ BRW_DOMAINS(INSTRUCTION, false)) >> 5;
}
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 1195f55..a3383ce 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -148,7 +148,7 @@ brw_upload_wm_unit(struct brw_context *brw)
brw->wm.base.state_offset + offsetof(struct brw_wm_unit_state, thread2),
brw->wm.base.scratch_bo,
wm->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER) >> 10;
+ BRW_DOMAINS(RENDER, true)) >> 10;
} else {
wm->thread2.scratch_space_base_pointer = 0;
wm->thread2.per_thread_scratch_space = 0;
@@ -177,7 +177,7 @@ brw_upload_wm_unit(struct brw_context *brw)
brw->wm.base.state_offset + offsetof(struct brw_wm_unit_state, wm4),
brw->batch.bo,
brw->wm.base.sampler_offset | wm->dw4,
- I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
+ BRW_DOMAINS(INSTRUCTION, false)) >> 5;
} else {
wm->wm4.sampler_state_pointer = 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f488557..1989e6d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -253,24 +253,20 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
6 * 4, 32, out_offset);
memset(surf, 0, 6 * 4);
+ /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
+ * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
+ * physical cache. It is mapped in hardware to the sampler cache."
+ */
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
(brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
bo, buffer_offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
+ BRW_DOMAINS(SAMPLER, rw));
surf[2] = (buffer_size & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
((buffer_size >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
surf[3] = ((buffer_size >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
(pitch - 1) << BRW_SURFACE_PITCH_SHIFT;
-
- /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
- * 5.1.2 "Data Cache" says: "the data cache does not exist as a separate
- * physical cache. It is mapped in hardware to the sampler cache."
- */
- if (bo) {
- }
}
void
@@ -365,11 +361,10 @@ brw_update_texture_surface(struct gl_context *ctx,
BRW_SURFACE_CUBEFACE_ENABLES |
tex_format << BRW_SURFACE_FORMAT_SHIFT);
- surf[1] = brw_batch_reloc(&brw->batch,
- *surf_offset + 4,
+ surf[1] = brw_batch_reloc(&brw->batch, *surf_offset + 4,
mt->bo,
mt->offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ BRW_DOMAINS(SAMPLER, false));
surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
(mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -475,11 +470,9 @@ brw_update_sol_surface(struct brw_context *brw,
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = brw_batch_reloc(&brw->batch,
- *out_offset + 4,
+ surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
bo, offset_bytes,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
@@ -595,8 +588,7 @@ brw_emit_null_surface_state(struct brw_context *brw,
}
surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
bo, 0,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -669,8 +661,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
mt->bo,
mt->offset +
intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y),
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 6aa772c..21212c8 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -69,13 +69,12 @@ gen6_blorp_emit_state_base_address(struct brw_context *brw,
1); /* GeneralStateBaseAddressModifyEnable */
/* SurfaceStateBaseAddress */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(SAMPLER, false), 1);
/* DynamicStateBaseAddress */
- OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
- I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false), 1);
OUT_BATCH(1); /* IndirectObjectBaseAddress */
if (params->use_wm_prog) {
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->cache.bo, BRW_DOMAINS(INSTRUCTION, false),
1); /* Instruction base address: shader kernels */
} else {
OUT_BATCH(1); /* InstructionBaseAddress */
@@ -115,10 +114,10 @@ gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
OUT_BATCH(dw0);
/* start address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(VERTEX, 0),
vertex_offset);
/* end address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(VERTEX, 0),
vertex_offset + vbo_size - 1);
OUT_BATCH(0);
ADVANCE_BATCH();
@@ -360,7 +359,7 @@ static uint32_t
gen6_blorp_emit_surface_state(struct brw_context *brw,
const brw_blorp_params *params,
const brw_blorp_surface_info *surface,
- uint32_t read_domains, uint32_t write_domain)
+ unsigned domains)
{
uint32_t wm_surf_offset;
uint32_t width = surface->width;
@@ -389,7 +388,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
wm_surf_offset + 4,
mt->bo,
surface->compute_tile_offsets(&tile_x, &tile_y),
- read_domains, write_domain);
+ domains);
surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
@@ -833,7 +832,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw2 */
OUT_RELOC(params->depth.mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
0);
/* 3DSTATE_DEPTH_BUFFER dw3 */
@@ -870,9 +869,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_mt->pitch - 1);
- OUT_RELOC(hiz_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ OUT_RELOC(hiz_mt->bo, BRW_DOMAINS(RENDER, true), offset);
ADVANCE_BATCH();
}
@@ -1040,12 +1037,11 @@ gen6_blorp_exec(struct brw_context *brw,
intel_miptree_used_for_rendering(params->dst.mt);
wm_surf_offset_renderbuffer =
gen6_blorp_emit_surface_state(brw, params, ¶ms->dst,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
if (params->src.mt) {
wm_surf_offset_texture =
gen6_blorp_emit_surface_state(brw, params, ¶ms->src,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ BRW_DOMAINS(SAMPLER, false));
}
wm_bind_bo_offset =
gen6_blorp_emit_binding_table(brw,
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index b1a9dd1..77e26d3 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -118,9 +118,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(depth_mt->bo, BRW_DOMAINS(RENDER, true), 0);
} else {
OUT_BATCH(0);
}
@@ -169,9 +167,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_mt->pitch - 1);
- OUT_RELOC(hiz_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ OUT_RELOC(hiz_mt->bo, BRW_DOMAINS(RENDER, true), offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
@@ -211,9 +207,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
* the stencil buffer is stored with two rows interleaved.
*/
OUT_BATCH(2 * stencil_mt->pitch - 1);
- OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ OUT_RELOC(stencil_mt->bo, BRW_DOMAINS(RENDER, true), offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 3d4bb68..02b34df 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -137,7 +137,7 @@ upload_gs_state(struct brw_context *brw)
if (prog_data->base.total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0); /* no scratch space */
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 120aedb..51e45fc 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -60,22 +60,22 @@ brw_store_register_mem64(struct brw_context *brw,
BEGIN_BATCH(8);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true),
idx * sizeof(uint64_t));
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true),
sizeof(uint32_t) + idx * sizeof(uint64_t));
ADVANCE_BATCH();
} else {
BEGIN_BATCH(6);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
idx * sizeof(uint64_t));
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
sizeof(uint32_t) + idx * sizeof(uint64_t));
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index 53abbba..2997221 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -96,8 +96,7 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
assert(mt->offset % mt->cpp == 0);
surf[1] = brw_batch_reloc(&brw->batch, offset + 4,
mt->bo, mt->offset,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
/* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
* (Surface Arrays For all surfaces other than separate stencil buffer):
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 89bb426..9535745 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -213,7 +213,7 @@ upload_vs_state(struct brw_context *brw)
if (brw->vs.prog_data->base.base.total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(brw->vs.prog_data->base.base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index e3b6054..96f9254 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -260,7 +260,7 @@ gen6_upload_wm_state(struct brw_context *brw,
OUT_BATCH(dw2);
if (prog_data->base.total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 62d735e..c9303fe 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -131,7 +131,7 @@ gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
static uint32_t
gen7_blorp_emit_surface_state(struct brw_context *brw,
const brw_blorp_surface_info *surface,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
bool is_render_target)
{
uint32_t wm_surf_offset;
@@ -171,7 +171,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
wm_surf_offset + 4,
mt->bo,
surface->compute_tile_offsets(&tile_x, &tile_y),
- read_domains, write_domain);
+ domains);
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
@@ -649,7 +649,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
1 << 28 | /* depth write */
surftype << 29);
OUT_RELOC(params->depth.mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
0);
OUT_BATCH((surfwidth - 1) << 4 |
(surfheight - 1) << 18 |
@@ -671,7 +671,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
OUT_BATCH((mocs << 25) |
(hiz_buf->pitch - 1));
OUT_RELOC(hiz_buf->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
0);
ADVANCE_BATCH();
}
@@ -795,13 +795,12 @@ gen7_blorp_exec(struct brw_context *brw,
intel_miptree_used_for_rendering(params->dst.mt);
wm_surf_offset_renderbuffer =
gen7_blorp_emit_surface_state(brw, ¶ms->dst,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
true /* is_render_target */);
if (params->src.mt) {
wm_surf_offset_texture =
gen7_blorp_emit_surface_state(brw, ¶ms->src,
- I915_GEM_DOMAIN_SAMPLER, 0,
+ BRW_DOMAINS(SAMPLER, false),
false /* is_render_target */);
}
wm_bind_bo_offset =
diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c
index 02add4c..dcbc7d0 100644
--- a/src/mesa/drivers/dri/i965/gen7_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c
@@ -62,7 +62,7 @@ upload_gs_state(struct brw_context *brw)
if (brw->gs.prog_data->base.base.total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(brw->gs.prog_data->base.base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index fb20b22..495dd94 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -113,9 +113,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(depth_mt->bo, BRW_DOMAINS(RENDER, true), 0);
} else {
OUT_BATCH(0);
}
@@ -150,10 +148,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
(hiz_buf->pitch - 1));
- OUT_RELOC(hiz_buf->bo,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(hiz_buf->bo, BRW_DOMAINS(RENDER, true), 0);
ADVANCE_BATCH();
}
@@ -181,9 +176,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(enabled |
mocs << 25 |
(2 * stencil_mt->pitch - 1));
- OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(stencil_mt->bo, BRW_DOMAINS(RENDER, true), 0);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index cabd77a..ff6678e 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -81,8 +81,8 @@ upload_3dstate_so_buffers(struct brw_context *brw)
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride);
- OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
- OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
+ OUT_RELOC(bo, BRW_DOMAINS(RENDER, true), start);
+ OUT_RELOC(bo, BRW_DOMAINS(RENDER, true), end);
ADVANCE_BATCH();
}
}
@@ -523,7 +523,7 @@ gen7_pause_transform_feedback(struct gl_context *ctx,
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_RELOC(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
i * sizeof(uint32_t));
ADVANCE_BATCH();
}
@@ -557,7 +557,7 @@ gen7_resume_transform_feedback(struct gl_context *ctx,
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_RELOC(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
i * sizeof(uint32_t));
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index b6e90bc..ef5a1b8 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -72,7 +72,7 @@ gen7_upload_constant_state(struct brw_context *brw,
/* XXX: When using buffers other than 0, you need to specify the
* graphics virtual address regardless of INSPM/debug bits
*/
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
+ OUT_RELOC64(brw->batch.bo, BRW_DOMAINS(RENDER, false),
stage_state->push_const_offset);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -128,7 +128,7 @@ upload_vs_state(struct brw_context *brw)
if (brw->vs.prog_data->base.base.total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(brw->vs.prog_data->base.base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 56400e3..55bd3b3 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -238,7 +238,7 @@ gen7_upload_ps_state(struct brw_context *brw,
OUT_BATCH(dw2);
if (prog_data->base.total_scratch) {
OUT_RELOC(brw->wm.base.scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 991e7bc..b9b8894 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -98,6 +98,8 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
const struct intel_mipmap_tree *mcs_mt,
bool is_render_target)
{
+ unsigned domains;
+
/* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
*
* "The MCS surface must be stored as Tile Y."
@@ -115,14 +117,15 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
* thus have their lower 12 bits zero), we can use an ordinary reloc to do
* the necessary address translation.
*/
+ domains = is_render_target ?
+ BRW_DOMAINS(RENDER, true) :
+ BRW_DOMAINS(SAMPLER, false);
surf[6] = brw_batch_reloc(&brw->batch,
surf_offset + 6 * 4,
mcs_mt->bo,
GEN7_SURFACE_MCS_ENABLE |
SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH),
- is_render_target ? I915_GEM_DOMAIN_RENDER
- : I915_GEM_DOMAIN_SAMPLER,
- is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
+ domains);
}
@@ -230,8 +233,8 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
+ bo, buffer_offset,
+ BRW_DOMAINS(SAMPLER, rw));
surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
if (surface_format == BRW_SURFACEFORMAT_RAW)
@@ -290,8 +293,7 @@ gen7_emit_texture_surface_state(struct brw_context *brw,
surf[1] = brw_batch_reloc(&brw->batch, *surf_offset + 4,
mt->bo, mt->offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
+ BRW_DOMAINS(SAMPLER, rw));
surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
@@ -505,8 +507,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
assert(mt->offset % mt->cpp == 0);
surf[1] = brw_batch_reloc(&brw->batch, offset + 4,
mt->bo, mt->offset,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
assert(brw->has_surface_tile_offset);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 739e974..82f4089 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -68,8 +68,7 @@ emit_depth_packets(struct brw_context *brw,
depthbuffer_format << 18 |
(depth_mt ? depth_mt->pitch - 1 : 0));
if (depth_mt) {
- OUT_RELOC64(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(depth_mt->bo, BRW_DOMAINS(RENDER, true), 0);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
@@ -92,8 +91,7 @@ emit_depth_packets(struct brw_context *brw,
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
- OUT_RELOC64(depth_mt->hiz_buf->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(depth_mt->hiz_buf->bo, BRW_DOMAINS(RENDER, true), 0);
OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
ADVANCE_BATCH();
}
@@ -125,8 +123,7 @@ emit_depth_packets(struct brw_context *brw,
*/
OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
(2 * stencil_mt->pitch - 1));
- OUT_RELOC64(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(stencil_mt->bo, BRW_DOMAINS(RENDER, true), 0);
OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index dc5e915..02a9d45 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -122,7 +122,7 @@ gen8_emit_vertices(struct brw_context *brw)
dw0 |= mocs_wb << 16;
OUT_BATCH(dw0);
- OUT_RELOC64(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
+ OUT_RELOC64(buffer->bo, BRW_DOMAINS(VERTEX, 0), buffer->offset);
OUT_BATCH(buffer->bo->size);
}
@@ -130,7 +130,7 @@ gen8_emit_vertices(struct brw_context *brw)
OUT_BATCH(brw->vb.nr_buffers << GEN6_VB0_INDEX_SHIFT |
GEN7_VB0_ADDRESS_MODIFYENABLE |
mocs_wb << 16);
- OUT_RELOC64(brw->draw.draw_params_bo, I915_GEM_DOMAIN_VERTEX, 0,
+ OUT_RELOC64(brw->draw.draw_params_bo, BRW_DOMAINS(VERTEX, 0),
brw->draw.draw_params_offset);
OUT_BATCH(brw->draw.draw_params_bo->size);
}
@@ -251,7 +251,7 @@ gen8_emit_index_buffer(struct brw_context *brw)
BEGIN_BATCH(5);
OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
OUT_BATCH(brw_get_index_type(index_buffer->type) | mocs_wb);
- OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+ OUT_RELOC64(brw->ib.bo, BRW_DOMAINS(VERTEX, 0), 0);
OUT_BATCH(brw->ib.bo->size);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index e5c3d23..f91d5d6 100644
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -55,7 +55,7 @@ gen8_upload_gs_state(struct brw_context *brw)
if (brw->gs.prog_data->base.base.total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(brw->gs.prog_data->base.base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index 83376cd..c0f951f 100644
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -40,17 +40,19 @@ void gen8_upload_state_base_address(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface state base address: */
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
+ OUT_RELOC64(brw->batch.bo,
+ BRW_DOMAINS(SAMPLER, false),
mocs_wb << 4 | 1);
/* Dynamic state base address: */
OUT_RELOC64(brw->batch.bo,
- I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BRW_DOMAINS(INSTRUCTION, false),
mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
- OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC64(brw->cache.bo,
+ BRW_DOMAINS(INSTRUCTION, 0),
mocs_wb << 4 | 1);
/* General state buffer size */
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 0c66e91..07e7a83 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -231,7 +231,7 @@ gen8_upload_ps_state(struct brw_context *brw,
OUT_BATCH(dw3);
if (prog_data->base.total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_sol_state.c b/src/mesa/drivers/dri/i965/gen8_sol_state.c
index 07212ab..fadf3dd 100644
--- a/src/mesa/drivers/dri/i965/gen8_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sol_state.c
@@ -81,10 +81,10 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE |
GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE |
(mocs_wb << 22));
- OUT_RELOC64(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
+ OUT_RELOC64(bo, BRW_DOMAINS(RENDER, true), start);
OUT_BATCH(xfb_obj->Size[i] / 4 - 1);
OUT_RELOC64(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
i * sizeof(uint32_t));
if (brw_obj->zero_offsets)
OUT_BATCH(0); /* Zero out the offset and write that to offset_bo */
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 2a815d7..23741fb 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -173,8 +173,7 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
/* Emit relocation to surface contents. */
*((uint64_t *)&surf[8]) =
brw_batch_reloc(&brw->batch, *out_offset + 8 * 4,
- bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
- rw ? I915_GEM_DOMAIN_SAMPLER : 0);
+ bo, buffer_offset, BRW_DOMAINS(SAMPLER, rw));
}
static void
@@ -273,14 +272,12 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
*((uint64_t *)&surf[8]) =
brw_batch_reloc(&brw->batch, *surf_offset + 8 * 4,
mt->bo, mt->offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
+ BRW_DOMAINS(SAMPLER, rw));
*((uint64_t *)&surf[10]) =
brw_batch_reloc(&brw->batch, *surf_offset + 10 * 4,
aux_mt ? aux_mt->bo : NULL, 0,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
+ BRW_DOMAINS(SAMPLER, rw));
surf[12] = 0;
}
@@ -491,13 +488,12 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
*((uint64_t *) &surf[8]) =
brw_batch_reloc(&brw->batch, offset + 8*4,
mt->bo, mt->offset,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
*((uint64_t *)&surf[10]) =
brw_batch_reloc(&brw->batch, offset + 10 * 4,
aux_mt ? aux_mt->bo : NULL, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
surf[12] = 0;
return offset;
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index f14951d..4b12326 100644
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -56,7 +56,7 @@ upload_vs_state(struct brw_context *brw)
if (prog_data->base.total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 1acbace..7e81685 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -651,24 +651,16 @@ intelEmitCopyBlit(struct brw_context *brw,
OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
if (brw->gen >= 8) {
- OUT_RELOC64(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC64(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
} else {
- OUT_RELOC(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
}
OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
OUT_BATCH((uint16_t)src_pitch);
if (brw->gen >= 8) {
- OUT_RELOC64(src_buffer,
- I915_GEM_DOMAIN_RENDER, 0,
- src_offset);
+ OUT_RELOC64(src_buffer, BRW_DOMAINS(RENDER, 0), src_offset);
} else {
- OUT_RELOC(src_buffer,
- I915_GEM_DOMAIN_RENDER, 0,
- src_offset);
+ OUT_RELOC(src_buffer, BRW_DOMAINS(RENDER, 0), src_offset);
}
ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
@@ -733,13 +725,9 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
if (brw->gen >= 8) {
- OUT_RELOC64(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC64(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
} else {
- OUT_RELOC(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
}
OUT_BATCH(0); /* bg */
OUT_BATCH(fg_color); /* fg */
@@ -861,13 +849,9 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
if (brw->gen >= 8) {
- OUT_RELOC64(mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC64(mt->bo, BRW_DOMAINS(RENDER, true), 0);
} else {
- OUT_RELOC(mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(mt->bo, BRW_DOMAINS(RENDER, true), 0);
}
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index c9a2007..a7b6056 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -87,7 +87,7 @@ can_do_pipelined_register_writes(struct brw_context *brw)
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
OUT_RELOC(brw->workaround_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
offset * sizeof(uint32_t));
ADVANCE_BATCH();
@@ -141,7 +141,7 @@ can_write_oacontrol(struct brw_context *brw)
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(OACONTROL);
OUT_RELOC(brw->workaround_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
offset * sizeof(uint32_t));
ADVANCE_BATCH();
--
2.1.4
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