[Mesa-dev] [PATCH 02/18] i965: Move pipecontrol workaround bo to brw_pipe_control
Martin Peres
martin.peres at linux.intel.com
Mon Jul 6 06:01:53 PDT 2015
On 06/07/15 13:33, Chris Wilson wrote:
> With the exception of gen8, the sole user of the workaround bo are for
> emitting pipe controls. Move it out of the purview of the batchbuffer
> and into the pipecontrol.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 7 +++++
> src/mesa/drivers/dri/i965/brw_context.h | 12 +++++---
> src/mesa/drivers/dri/i965/brw_pipe_control.c | 40 +++++++++++++++++++++++----
> src/mesa/drivers/dri/i965/gen8_depth_state.c | 2 +-
> src/mesa/drivers/dri/i965/intel_batchbuffer.c | 12 --------
> src/mesa/drivers/dri/i965/intel_extensions.c | 28 +++++++++----------
> 6 files changed, 64 insertions(+), 37 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 4b51fe5..8150b94 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -819,6 +819,12 @@ brwCreateContext(gl_api api,
> }
> }
>
> + if (brw_init_pipe_control(brw, devinfo)) {
> + *dri_ctx_error = __DRI_CTX_ERROR_NO_MEMORY;
> + intelDestroyContext(driContextPriv);
> + return false;
> + }
> +
> brw_init_state(brw);
>
> intelInitExtensions(ctx);
> @@ -942,6 +948,7 @@ intelDestroyContext(__DRIcontext * driContextPriv)
> if (ctx->swrast_context)
> _swrast_DestroyContext(&brw->ctx);
>
> + brw_fini_pipe_control(brw);
> intel_batchbuffer_free(brw);
>
> drm_intel_bo_unreference(brw->throttle_batch[1]);
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
> index 3553f6e..db0fc48 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -868,8 +868,6 @@ struct intel_batchbuffer {
> drm_intel_bo *bo;
> /** Last BO submitted to the hardware. Used for glFinish(). */
> drm_intel_bo *last_bo;
> - /** BO for post-sync nonzero writes for gen6 workaround. */
> - drm_intel_bo *workaround_bo;
>
> uint16_t emit, total;
> uint16_t used, reserved_space;
> @@ -881,8 +879,6 @@ struct intel_batchbuffer {
> enum brw_gpu_ring ring;
> bool needs_sol_reset;
>
> - uint8_t pipe_controls_since_last_cs_stall;
> -
> struct {
> uint16_t used;
> int reloc_count;
> @@ -1034,6 +1030,10 @@ struct brw_context
>
> drm_intel_context *hw_ctx;
>
> + /** BO for post-sync nonzero writes for gen6 workaround. */
> + drm_intel_bo *workaround_bo;
> + uint8_t pipe_controls_since_last_cs_stall;
> +
> /**
> * Set of drm_intel_bo * that have been rendered to within this batchbuffer
> * and would need flushing before being used from another cache domain that
> @@ -2000,6 +2000,10 @@ gen9_use_linear_1d_layout(const struct brw_context *brw,
> const struct intel_mipmap_tree *mt);
>
> /* brw_pipe_control.c */
> +int brw_init_pipe_control(struct brw_context *brw,
> + const struct brw_device_info *info);
> +void brw_fini_pipe_control(struct brw_context *brw);
> +
> void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
> void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
> drm_intel_bo *bo, uint32_t offset,
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index b4c86b9..7ee3cb6 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -72,13 +72,13 @@ gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
> if (brw->gen == 7 && !brw->is_haswell) {
> if (flags & PIPE_CONTROL_CS_STALL) {
> /* If we're doing a CS stall, reset the counter and carry on. */
> - brw->batch.pipe_controls_since_last_cs_stall = 0;
> + brw->pipe_controls_since_last_cs_stall = 0;
> return 0;
> }
>
> /* If this is the fourth pipe control without a CS stall, do one now. */
> - if (++brw->batch.pipe_controls_since_last_cs_stall == 4) {
> - brw->batch.pipe_controls_since_last_cs_stall = 0;
> + if (++brw->pipe_controls_since_last_cs_stall == 4) {
> + brw->pipe_controls_since_last_cs_stall = 0;
> return PIPE_CONTROL_CS_STALL;
> }
> }
> @@ -213,7 +213,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
> brw_emit_pipe_control_write(brw,
> PIPE_CONTROL_WRITE_IMMEDIATE
> | PIPE_CONTROL_DEPTH_STALL,
> - brw->batch.workaround_bo, 0,
> + brw->workaround_bo, 0,
> 0, 0);
> }
>
> @@ -227,7 +227,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
> brw_emit_pipe_control_write(brw,
> PIPE_CONTROL_CS_STALL
> | PIPE_CONTROL_WRITE_IMMEDIATE,
> - brw->batch.workaround_bo, 0,
> + brw->workaround_bo, 0,
> 0, 0);
> }
>
> @@ -277,7 +277,7 @@ brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
> PIPE_CONTROL_STALL_AT_SCOREBOARD);
>
> brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
> - brw->batch.workaround_bo, 0, 0, 0);
> + brw->workaround_bo, 0, 0, 0);
> }
>
> /* Emit a pipelined flush to either flush render and texture cache for
> @@ -329,3 +329,31 @@ brw_emit_mi_flush(struct brw_context *brw)
>
> brw_render_cache_set_clear(brw);
> }
> +
> +int
> +brw_init_pipe_control(struct brw_context *brw,
> + const struct brw_device_info *devinfo)
> +{
> + if (devinfo->gen < 6)
> + return 0;
> +
> + /* We can't just use brw_state_batch to get a chunk of space for
> + * the gen6 workaround because it involves actually writing to
> + * the buffer, and the kernel doesn't let us write to the batch.
> + */
> + brw->workaround_bo = drm_intel_bo_alloc(brw->bufmgr,
> + "pipe_control workaround",
> + 4096, 4096);
> + if (brw->workaround_bo == NULL)
> + return -ENOMEM;
> +
> + brw->pipe_controls_since_last_cs_stall = 0;
> +
> + return 0;
> +}
> +
> +void
> +brw_fini_pipe_control(struct brw_context *brw)
> +{
> + drm_intel_bo_unreference(brw->workaround_bo);
> +}
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index bc05a31..8f23702 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -496,7 +496,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
> */
> brw_emit_pipe_control_write(brw,
> PIPE_CONTROL_WRITE_IMMEDIATE,
> - brw->batch.workaround_bo, 0, 0, 0);
> + brw->workaround_bo, 0, 0, 0);
>
> /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
> BEGIN_BATCH(5);
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 54081a1..969d92c 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -44,16 +44,6 @@ intel_batchbuffer_init(struct brw_context *brw)
> {
> intel_batchbuffer_reset(brw);
>
> - if (brw->gen >= 6) {
> - /* We can't just use brw_state_batch to get a chunk of space for
> - * the gen6 workaround because it involves actually writing to
> - * the buffer, and the kernel doesn't let us write to the batch.
> - */
> - brw->batch.workaround_bo = drm_intel_bo_alloc(brw->bufmgr,
> - "pipe_control workaround",
> - 4096, 4096);
> - }
> -
> if (!brw->has_llc) {
> brw->batch.cpu_map = malloc(BATCH_SZ);
> brw->batch.map = brw->batch.cpu_map;
> @@ -82,7 +72,6 @@ intel_batchbuffer_reset(struct brw_context *brw)
> brw->batch.state_batch_offset = brw->batch.bo->size;
> brw->batch.used = 0;
> brw->batch.needs_sol_reset = false;
> - brw->batch.pipe_controls_since_last_cs_stall = 0;
>
> /* We don't know what ring the new batch will be sent to until we see the
> * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
> @@ -114,7 +103,6 @@ intel_batchbuffer_free(struct brw_context *brw)
> free(brw->batch.cpu_map);
> drm_intel_bo_unreference(brw->batch.last_bo);
> drm_intel_bo_unreference(brw->batch.bo);
> - drm_intel_bo_unreference(brw->batch.workaround_bo);
> }
>
> static void
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
> index 740ac81..6b3bd12 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -64,10 +64,10 @@ can_do_pipelined_register_writes(struct brw_context *brw)
> /* Set a value in a BO to a known quantity. The workaround BO already
> * exists and doesn't contain anything important, so we may as well use it.
> */
> - drm_intel_bo_map(brw->batch.workaround_bo, true);
> - data = brw->batch.workaround_bo->virtual;
> + drm_intel_bo_map(brw->workaround_bo, true);
> + data = brw->workaround_bo->virtual;
> data[offset] = 0xffffffff;
> - drm_intel_bo_unmap(brw->batch.workaround_bo);
> + drm_intel_bo_unmap(brw->workaround_bo);
>
> /* Write the register. */
> BEGIN_BATCH(3);
> @@ -82,7 +82,7 @@ can_do_pipelined_register_writes(struct brw_context *brw)
> BEGIN_BATCH(3);
> OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
> OUT_BATCH(reg);
> - OUT_RELOC(brw->batch.workaround_bo,
> + OUT_RELOC(brw->workaround_bo,
> I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> offset * sizeof(uint32_t));
> ADVANCE_BATCH();
> @@ -90,10 +90,10 @@ can_do_pipelined_register_writes(struct brw_context *brw)
> intel_batchbuffer_flush(brw);
>
> /* Check whether the value got written. */
> - drm_intel_bo_map(brw->batch.workaround_bo, false);
> - data = brw->batch.workaround_bo->virtual;
> + drm_intel_bo_map(brw->workaround_bo, false);
> + data = brw->workaround_bo->virtual;
> bool success = data[offset] == expected_value;
> - drm_intel_bo_unmap(brw->batch.workaround_bo);
> + drm_intel_bo_unmap(brw->workaround_bo);
>
> result = success;
>
> @@ -120,10 +120,10 @@ can_write_oacontrol(struct brw_context *brw)
> /* Set a value in a BO to a known quantity. The workaround BO already
> * exists and doesn't contain anything important, so we may as well use it.
> */
> - drm_intel_bo_map(brw->batch.workaround_bo, true);
> - data = brw->batch.workaround_bo->virtual;
> + drm_intel_bo_map(brw->workaround_bo, true);
> + data = brw->workaround_bo->virtual;
> data[offset] = 0xffffffff;
> - drm_intel_bo_unmap(brw->batch.workaround_bo);
> + drm_intel_bo_unmap(brw->workaround_bo);
>
> /* Write OACONTROL. */
> BEGIN_BATCH(3);
> @@ -138,7 +138,7 @@ can_write_oacontrol(struct brw_context *brw)
> BEGIN_BATCH(3);
> OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
> OUT_BATCH(OACONTROL);
> - OUT_RELOC(brw->batch.workaround_bo,
> + OUT_RELOC(brw->workaround_bo,
> I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
> offset * sizeof(uint32_t));
> ADVANCE_BATCH();
> @@ -155,10 +155,10 @@ can_write_oacontrol(struct brw_context *brw)
> intel_batchbuffer_flush(brw);
>
> /* Check whether the value got written. */
> - drm_intel_bo_map(brw->batch.workaround_bo, false);
> - data = brw->batch.workaround_bo->virtual;
> + drm_intel_bo_map(brw->workaround_bo, false);
> + data = brw->workaround_bo->virtual;
> bool success = data[offset] == expected_value;
> - drm_intel_bo_unmap(brw->batch.workaround_bo);
> + drm_intel_bo_unmap(brw->workaround_bo);
>
> result = success;
>
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