[Mesa-dev] [PATCH 3/3] i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.

[Matt Turner]

On Mon, Jul 6, 2015 at 11:03 AM, Francisco Jerez <currojerez at riseup.net> wrote:
> This was probably disabled due to a combination of several bugs in the
> generator code (fixed earlier in this series) and a misunderstanding
> of the hardware spec.  The documentation for most control flow
> instructions mentions among other restrictions:
>
>  "Instruction compression is not allowed."
>
> This however doesn't have any implications on 16 wide not being
> supported, because none of the control flow instructions have
> multi-register operands (control flow instructions are not compressed
> on more recent hardware either, except maybe SNB's IF with inline
> compare).  In fact Gen4-5 had 16-wide control flow masks and stacks,
> and the spec mentions in several places that control flow instructions
> push and pop 16 channels worth of data -- Otherwise there doesn't seem
> to be any indication that it shouldn't work.

Awesome. Yeah, I was wondering aloud to Ken recently about what
actually prevented non-uniform control flow from working -- because as
you say the mask registers are 16-channels wide.

Really cool to find out that it was just a couple of bugs and nothing
fundamental. Really nice work.

> Causes no piglit regressions, and gives the following shader-db
> results on ILK:

Assuming no regressions on Gen4 and G45 (running through Jenkins should do it):

Reviewed-by: Matt Turner <mattst88 at gmail.com>