[Mesa-dev] [PATCH 3/5] i965: Turn set_blitter_tiling() into a macro.

[Matt Turner]

Its uses of OUT_BATCH will need a local variable defined by BEGIN_BATCH.

Increases .text size by 528 bytes.
---
 src/mesa/drivers/dri/i965/intel_blit.c | 55 ++++++++++++++++------------------
 1 file changed, 25 insertions(+), 30 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index bc39053..2a0f621 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -176,36 +176,31 @@ get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
  * tiling state would leak into other unsuspecting applications (like the X
  * server).
  */
-static void
-set_blitter_tiling(struct brw_context *brw,
-                   bool dst_y_tiled, bool src_y_tiled)
-{
-   assert(brw->gen >= 6);
-
-   /* Idle the blitter before we update how tiling is interpreted. */
-   OUT_BATCH(MI_FLUSH_DW);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-
-   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-   OUT_BATCH(BCS_SWCTRL);
-   OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
-             (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
-             (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
-}
-
-#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do {         \
-      BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
-      if (dst_y_tiled || src_y_tiled)                                   \
-         set_blitter_tiling(brw, dst_y_tiled, src_y_tiled);             \
-   } while (0)
-
-#define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do {              \
-      if (dst_y_tiled || src_y_tiled)                                   \
-         set_blitter_tiling(brw, false, false);                         \
-      ADVANCE_BATCH();                                                  \
-   } while (0)
+#define SET_BLITTER_TILING(dst_y_tiled, src_y_tiled) do {             \
+   assert(brw->gen >= 6);                                             \
+                                                                      \
+   /* Idle the blitter before we update how tiling is interpreted. */ \
+   OUT_BATCH(MI_FLUSH_DW);                                            \
+   OUT_BATCH(0);                                                      \
+   OUT_BATCH(0);                                                      \
+   OUT_BATCH(0);                                                      \
+                                                                      \
+   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));                         \
+   OUT_BATCH(BCS_SWCTRL);                                             \
+   OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |            \
+             (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |                   \
+             (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));                   \
+} while (0)
+
+#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)        \
+   BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));  \
+   if (dst_y_tiled || src_y_tiled)                                \
+      SET_BLITTER_TILING(dst_y_tiled, src_y_tiled)                \
+
+#define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled)             \
+   if (dst_y_tiled || src_y_tiled)                                \
+      SET_BLITTER_TILING(false, false);                           \
+   ADVANCE_BATCH()
 
 static int
 blt_pitch(struct intel_mipmap_tree *mt)
-- 
2.3.6