[Mesa-dev] [PATCH 4/4] r200: fix some potential big endian issues
sroland at vmware.com
sroland at vmware.com
Sat Jul 11 11:39:47 PDT 2015
From: Roland Scheidegger <sroland at vmware.com>
The formats chosen (both by texture format choser, fbo storage allocation)
are different for big endian not just for rgba8 but also lower bit width
formats (why I don't actually know). Even the function to test for renderable
formats used different formats, however the actual colorbuffer setup did not.
And the blitter did not take that into account neither.
Untested (what could possibly go wrong...).
Same as for r100.
---
src/mesa/drivers/dri/r200/r200_blit.c | 118 +++++++++++++++-------------
src/mesa/drivers/dri/r200/r200_context.h | 4 -
src/mesa/drivers/dri/r200/r200_state_init.c | 5 +-
src/mesa/drivers/dri/r200/r200_tex.h | 64 +++++++++++++++
src/mesa/drivers/dri/r200/r200_texstate.c | 71 -----------------
5 files changed, 133 insertions(+), 129 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c
index 0e6afa0..0cab84b 100644
--- a/src/mesa/drivers/dri/r200/r200_blit.c
+++ b/src/mesa/drivers/dri/r200/r200_blit.c
@@ -28,6 +28,7 @@
#include "radeon_common.h"
#include "r200_context.h"
#include "r200_blit.h"
+#include "r200_tex.h"
static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
int reg, int count)
@@ -40,22 +41,42 @@ static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
/* common formats supported as both textures and render targets */
unsigned r200_check_blit(mesa_format mesa_format, uint32_t dst_pitch)
{
- /* XXX others? BE/LE? */
- switch (mesa_format) {
- case MESA_FORMAT_B8G8R8A8_UNORM:
- case MESA_FORMAT_B8G8R8X8_UNORM:
- case MESA_FORMAT_B5G6R5_UNORM:
- case MESA_FORMAT_B4G4R4A4_UNORM:
- case MESA_FORMAT_B5G5R5A1_UNORM:
- case MESA_FORMAT_A_UNORM8:
- case MESA_FORMAT_L_UNORM8:
- case MESA_FORMAT_I_UNORM8:
- /* swizzled */
- case MESA_FORMAT_A8B8G8R8_UNORM:
- case MESA_FORMAT_R8G8B8A8_UNORM:
+ /* XXX others? */
+ if (_mesa_little_endian()) {
+ switch (mesa_format) {
+ case MESA_FORMAT_B8G8R8A8_UNORM:
+ case MESA_FORMAT_B8G8R8X8_UNORM:
+ case MESA_FORMAT_B5G6R5_UNORM:
+ case MESA_FORMAT_B4G4R4A4_UNORM:
+ case MESA_FORMAT_B5G5R5A1_UNORM:
+ case MESA_FORMAT_A_UNORM8:
+ case MESA_FORMAT_L_UNORM8:
+ case MESA_FORMAT_I_UNORM8:
+ /* swizzled */
+ case MESA_FORMAT_A8B8G8R8_UNORM:
+ case MESA_FORMAT_R8G8B8A8_UNORM:
break;
- default:
+ default:
return 0;
+ }
+ }
+ else {
+ switch (mesa_format) {
+ case MESA_FORMAT_A8R8G8B8_UNORM:
+ case MESA_FORMAT_X8R8G8B8_UNORM:
+ case MESA_FORMAT_R5G6B5_UNORM:
+ case MESA_FORMAT_A4R4G4B4_UNORM:
+ case MESA_FORMAT_A1R5G5B5_UNORM:
+ case MESA_FORMAT_A_UNORM8:
+ case MESA_FORMAT_L_UNORM8:
+ case MESA_FORMAT_I_UNORM8:
+ /* swizzled */
+ case MESA_FORMAT_R8G8B8A8_UNORM:
+ case MESA_FORMAT_A8B8G8R8_UNORM:
+ break;
+ default:
+ return 0;
+ }
}
/* Rendering to small buffer doesn't work.
@@ -112,41 +133,11 @@ static void inline emit_tx_setup(struct r200_context *r200,
assert(height <= 2048);
assert(offset % 32 == 0);
- /* XXX others? BE/LE? */
- switch (src_mesa_format) {
- case MESA_FORMAT_B8G8R8A8_UNORM:
- txformat |= R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP;
- break;
- case MESA_FORMAT_A8B8G8R8_UNORM:
- txformat |= R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP;
- break;
- case MESA_FORMAT_R8G8B8A8_UNORM:
- txformat |= R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP;
- break;
- case MESA_FORMAT_B8G8R8X8_UNORM:
- txformat |= R200_TXFORMAT_ARGB8888;
- break;
- case MESA_FORMAT_B5G6R5_UNORM:
- txformat |= R200_TXFORMAT_RGB565;
- break;
- case MESA_FORMAT_B4G4R4A4_UNORM:
- txformat |= R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP;
- break;
- case MESA_FORMAT_B5G5R5A1_UNORM:
- txformat |= R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP;
- break;
- case MESA_FORMAT_A_UNORM8:
- case MESA_FORMAT_I_UNORM8:
- txformat |= R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP;
- break;
- case MESA_FORMAT_L_UNORM8:
- txformat |= R200_TXFORMAT_I8;
- break;
- case MESA_FORMAT_L8A8_UNORM:
- txformat |= R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP;
- break;
- default:
- break;
+ if (_mesa_little_endian()) {
+ txformat |= tx_table_le[src_mesa_format].format;
+ }
+ else {
+ txformat |= tx_table_be[src_mesa_format].format;
}
if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
@@ -155,11 +146,19 @@ static void inline emit_tx_setup(struct r200_context *r200,
offset |= R200_TXO_MICRO_TILE;
switch (dst_mesa_format) {
+ /* le */
case MESA_FORMAT_B8G8R8A8_UNORM:
case MESA_FORMAT_B8G8R8X8_UNORM:
case MESA_FORMAT_B5G6R5_UNORM:
case MESA_FORMAT_B4G4R4A4_UNORM:
case MESA_FORMAT_B5G5R5A1_UNORM:
+ /* be */
+ case MESA_FORMAT_A8R8G8B8_UNORM:
+ case MESA_FORMAT_X8R8G8B8_UNORM:
+ case MESA_FORMAT_R5G6B5_UNORM:
+ case MESA_FORMAT_A4R4G4B4_UNORM:
+ case MESA_FORMAT_A1R5G5B5_UNORM:
+ /* little and big */
case MESA_FORMAT_A_UNORM8:
case MESA_FORMAT_L_UNORM8:
case MESA_FORMAT_I_UNORM8:
@@ -183,6 +182,9 @@ static void inline emit_tx_setup(struct r200_context *r200,
END_BATCH();
break;
case MESA_FORMAT_A8B8G8R8_UNORM:
+ case MESA_FORMAT_R8G8B8A8_UNORM:
+ if ((dst_mesa_format == MESA_FORMAT_A8B8G8R8_UNORM && _mesa_little_endian()) ||
+ (dst_mesa_format == MESA_FORMAT_R8G8B8A8_UNORM && !_mesa_little_endian())) {
BEGIN_BATCH(10);
OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
RADEON_TEX_BLEND_0_ENABLE));
@@ -190,6 +192,8 @@ static void inline emit_tx_setup(struct r200_context *r200,
R200_TXC_ARG_B_ZERO |
R200_TXC_ARG_C_R0_COLOR |
R200_TXC_OP_MADD));
+ /* XXX I don't think this can work. This is output rotation, and alpha contains
+ * red, not alpha (we'd write gbrr). */
OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
R200_TXC_OUTPUT_ROTATE_GBA |
R200_TXC_OUTPUT_REG_R0));
@@ -201,8 +205,8 @@ static void inline emit_tx_setup(struct r200_context *r200,
(R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) |
R200_TXA_OUTPUT_REG_R0));
END_BATCH();
- break;
- case MESA_FORMAT_R8G8B8A8_UNORM:
+ }
+ else {
BEGIN_BATCH(34);
OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
RADEON_TEX_BLEND_0_ENABLE |
@@ -272,7 +276,8 @@ static void inline emit_tx_setup(struct r200_context *r200,
OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 |
R200_TXA_OUTPUT_REG_R0));
END_BATCH();
- break;
+ }
+ break;
}
BEGIN_BATCH(18);
@@ -306,21 +311,28 @@ static inline void emit_cb_setup(struct r200_context *r200,
uint32_t dst_format = 0;
BATCH_LOCALS(&r200->radeon);
- /* XXX others? BE/LE? */
switch (mesa_format) {
+ /* le */
case MESA_FORMAT_B8G8R8A8_UNORM:
case MESA_FORMAT_B8G8R8X8_UNORM:
+ /* le/be */
case MESA_FORMAT_A8B8G8R8_UNORM:
case MESA_FORMAT_R8G8B8A8_UNORM:
+ /* be */
+ case MESA_FORMAT_A8R8G8B8_UNORM:
+ case MESA_FORMAT_X8R8G8B8_UNORM:
dst_format = RADEON_COLOR_FORMAT_ARGB8888;
break;
case MESA_FORMAT_B5G6R5_UNORM:
+ case MESA_FORMAT_R5G6B5_UNORM:
dst_format = RADEON_COLOR_FORMAT_RGB565;
break;
case MESA_FORMAT_B4G4R4A4_UNORM:
+ case MESA_FORMAT_A4R4G4B4_UNORM:
dst_format = RADEON_COLOR_FORMAT_ARGB4444;
break;
case MESA_FORMAT_B5G5R5A1_UNORM:
+ case MESA_FORMAT_A1R5G5B5_UNORM:
dst_format = RADEON_COLOR_FORMAT_ARGB1555;
break;
case MESA_FORMAT_A_UNORM8:
diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index eb498f7..e8784ae 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -109,7 +109,6 @@ struct r200_texture_state {
#define CTX_RB3D_COLOROFFSET 11
#define CTX_CMD_2 12 /* why */
#define CTX_RB3D_COLORPITCH 13 /* why */
-#define CTX_STATE_SIZE_OLDDRM 14
#define CTX_CMD_3 14
#define CTX_RB3D_BLENDCOLOR 15
#define CTX_RB3D_ABLENDCNTL 16
@@ -167,9 +166,6 @@ struct r200_texture_state {
#define TEX_PP_TXSIZE 4 /*2c0c*/
#define TEX_PP_TXPITCH 5 /*2c10*/
#define TEX_PP_BORDER_COLOR 6 /*2c14*/
-#define TEX_CMD_1_OLDDRM 7
-#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */
-#define TEX_STATE_SIZE_OLDDRM 9
#define TEX_PP_CUBIC_FACES 7
#define TEX_PP_TXMULTI_CTL 8
#define TEX_CMD_1_NEWDRM 9
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c
index d9d1a0e..ad64f78 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -254,7 +254,7 @@ CHECK( never, GL_FALSE, 0 )
CHECK( tex_any, ctx->Texture._MaxEnabledTexImageUnit != -1, 0 )
CHECK( tf, (ctx->Texture._MaxEnabledTexImageUnit != -1 && !ctx->ATIFragmentShader._Enabled), 0 );
CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 )
- CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 )
+CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 )
CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
@@ -453,12 +453,15 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
else switch (rrb->base.Base.Format) {
case MESA_FORMAT_B5G6R5_UNORM:
+ case MESA_FORMAT_R5G6B5_UNORM:
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
break;
case MESA_FORMAT_B4G4R4A4_UNORM:
+ case MESA_FORMAT_A4R4G4B4_UNORM:
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
break;
case MESA_FORMAT_B5G5R5A1_UNORM:
+ case MESA_FORMAT_A1R5G5B5_UNORM:
atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
break;
default:
diff --git a/src/mesa/drivers/dri/r200/r200_tex.h b/src/mesa/drivers/dri/r200/r200_tex.h
index d7e91d1..a8c31b7 100644
--- a/src/mesa/drivers/dri/r200/r200_tex.h
+++ b/src/mesa/drivers/dri/r200/r200_tex.h
@@ -52,4 +52,68 @@ extern void r200TexUpdateParameters(struct gl_context *ctx, GLuint unit);
extern void set_re_cntl_d3d( struct gl_context *ctx, int unit, GLboolean use_d3d );
+struct tx_table {
+ GLuint format, filter;
+};
+
+/* Note the tables (have to) contain invalid entries (if they are only valid
+ * for either be/le) */
+static const struct tx_table tx_table_be[] =
+{
+ [ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_BGR_UNORM8 ] = { 0xffffffff, 0 },
+ [ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
+ [ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
+ [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A4R4G4B4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_B5G5R5A1_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A1R5G5B5_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_L8A8_UNORM ] = { R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A8L8_UNORM ] = { R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_L_UNORM8 ] = { R200_TXFORMAT_I8, 0 },
+ [ MESA_FORMAT_I_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_YCBCR ] = { R200_TXFORMAT_YVYU422, R200_YUV_TO_RGB },
+ [ MESA_FORMAT_YCBCR_REV ] = { R200_TXFORMAT_VYUY422, R200_YUV_TO_RGB },
+ [ MESA_FORMAT_RGB_FXT1 ] = { 0xffffffff, 0 },
+ [ MESA_FORMAT_RGBA_FXT1 ] = { 0xffffffff, 0 },
+ [ MESA_FORMAT_RGB_DXT1 ] = { R200_TXFORMAT_DXT1, 0 },
+ [ MESA_FORMAT_RGBA_DXT1 ] = { R200_TXFORMAT_DXT1 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_RGBA_DXT3 ] = { R200_TXFORMAT_DXT23 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_RGBA_DXT5 ] = { R200_TXFORMAT_DXT45 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+};
+
+static const struct tx_table tx_table_le[] =
+{
+ [ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_BGR_UNORM8 ] = { R200_TXFORMAT_ARGB8888, 0 },
+ [ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
+ [ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
+ [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A4R4G4B4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_B5G5R5A1_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A1R5G5B5_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_L8A8_UNORM ] = { R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A8L8_UNORM ] = { R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_A_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_L_UNORM8 ] = { R200_TXFORMAT_I8, 0 },
+ [ MESA_FORMAT_I_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_YCBCR ] = { R200_TXFORMAT_YVYU422, R200_YUV_TO_RGB },
+ [ MESA_FORMAT_YCBCR_REV ] = { R200_TXFORMAT_VYUY422, R200_YUV_TO_RGB },
+ [ MESA_FORMAT_RGB_FXT1 ] = { 0xffffffff, 0 },
+ [ MESA_FORMAT_RGBA_FXT1 ] = { 0xffffffff, 0 },
+ [ MESA_FORMAT_RGB_DXT1 ] = { R200_TXFORMAT_DXT1, 0 },
+ [ MESA_FORMAT_RGBA_DXT1 ] = { R200_TXFORMAT_DXT1 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_RGBA_DXT3 ] = { R200_TXFORMAT_DXT23 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+ [ MESA_FORMAT_RGBA_DXT5 ] = { R200_TXFORMAT_DXT45 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+};
+
+
+
#endif /* __R200_TEX_H__ */
diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index ab84d17..441ac73 100644
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -49,80 +49,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r200_tex.h"
#include "r200_tcl.h"
-
-#define R200_TXFORMAT_A8 R200_TXFORMAT_I8
-#define R200_TXFORMAT_L8 R200_TXFORMAT_I8
-#define R200_TXFORMAT_AL88 R200_TXFORMAT_AI88
-#define R200_TXFORMAT_YCBCR R200_TXFORMAT_YVYU422
-#define R200_TXFORMAT_YCBCR_REV R200_TXFORMAT_VYUY422
-#define R200_TXFORMAT_RGB_DXT1 R200_TXFORMAT_DXT1
-#define R200_TXFORMAT_RGBA_DXT1 R200_TXFORMAT_DXT1
-#define R200_TXFORMAT_RGBA_DXT3 R200_TXFORMAT_DXT23
-#define R200_TXFORMAT_RGBA_DXT5 R200_TXFORMAT_DXT45
-
#define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
&& (tx_table_be[f].format != 0xffffffff) )
-struct tx_table {
- GLuint format, filter;
-};
-
-static const struct tx_table tx_table_be[] =
-{
- [ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_BGR_UNORM8 ] = { 0xffffffff, 0 },
- [ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
- [ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
- [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A4R4G4B4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_B5G5R5A1_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A1R5G5B5_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_L8A8_UNORM ] = { R200_TXFORMAT_AL88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A8L8_UNORM ] = { R200_TXFORMAT_AL88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A_UNORM8 ] = { R200_TXFORMAT_A8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_L_UNORM8 ] = { R200_TXFORMAT_L8, 0 },
- [ MESA_FORMAT_I_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_YCBCR ] = { R200_TXFORMAT_YCBCR, R200_YUV_TO_RGB },
- [ MESA_FORMAT_YCBCR_REV ] = { R200_TXFORMAT_YCBCR_REV, R200_YUV_TO_RGB },
- [ MESA_FORMAT_RGB_FXT1 ] = { 0xffffffff, 0 },
- [ MESA_FORMAT_RGBA_FXT1 ] = { 0xffffffff, 0 },
- [ MESA_FORMAT_RGB_DXT1 ] = { R200_TXFORMAT_RGB_DXT1, 0 },
- [ MESA_FORMAT_RGBA_DXT1 ] = { R200_TXFORMAT_RGBA_DXT1 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_RGBA_DXT3 ] = { R200_TXFORMAT_RGBA_DXT3 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_RGBA_DXT5 ] = { R200_TXFORMAT_RGBA_DXT5 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
-};
-
-static const struct tx_table tx_table_le[] =
-{
- [ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_BGR_UNORM8 ] = { R200_TXFORMAT_ARGB8888, 0 },
- [ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
- [ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
- [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A4R4G4B4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_B5G5R5A1_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A1R5G5B5_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_L8A8_UNORM ] = { R200_TXFORMAT_AL88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A8L8_UNORM ] = { R200_TXFORMAT_AL88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_A_UNORM8 ] = { R200_TXFORMAT_A8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_L_UNORM8 ] = { R200_TXFORMAT_L8, 0 },
- [ MESA_FORMAT_I_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_YCBCR ] = { R200_TXFORMAT_YCBCR, R200_YUV_TO_RGB },
- [ MESA_FORMAT_YCBCR_REV ] = { R200_TXFORMAT_YCBCR_REV, R200_YUV_TO_RGB },
- [ MESA_FORMAT_RGB_FXT1 ] = { 0xffffffff, 0 },
- [ MESA_FORMAT_RGBA_FXT1 ] = { 0xffffffff, 0 },
- [ MESA_FORMAT_RGB_DXT1 ] = { R200_TXFORMAT_RGB_DXT1, 0 },
- [ MESA_FORMAT_RGBA_DXT1 ] = { R200_TXFORMAT_RGBA_DXT1 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_RGBA_DXT3 ] = { R200_TXFORMAT_RGBA_DXT3 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
- [ MESA_FORMAT_RGBA_DXT5 ] = { R200_TXFORMAT_RGBA_DXT5 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
-};
-
/* ================================================================
* Texture combine functions
*/
--
2.1.4
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