[Mesa-dev] radeonsi indirect sampler, llvm backend issue

[Dave Airlie]

Hey,

So i tried to get ARB_gpu_shader5 indirect sampler support to work in radeonsi,

The attached patch to mesa adds support, but the llvm backend appears
to do the wrong thing, and I'm not sure how to fix it.

So the image sampling functions needs the resource and sampler address in SGPR,

So I generate a load of v8i32 for the resource, and v4i32 for the
sampler, however the backend translate the v4i32 load into a VGPR
based load, then it all chokes when it tries to pass that to the image
sample.

commenting out the following pattern in the backend makes things work
as a workaround.
defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;
I then get an s_load_dwordx4 instead of a buffer_load_dwordx4.

I've exhausted my knowledge of llvm already on this, so any ideas let me know.

Below is the tgsi/llvm inputs I create.

Dave.

FRAG
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SVIEW[0], 2D, FLOAT
DCL SVIEW[1], 2D, FLOAT
DCL SVIEW[2], 2D, FLOAT
DCL SVIEW[3], 2D, FLOAT
DCL CONST[4]
DCL TEMP[0], LOCAL
DCL ADDR[0..2]
IMM[0] FLT32 {    0.7500,     0.2500,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IMM[0].xyyy
  1: UARL ADDR[2].x, CONST[4].xxxx
  2: TEX TEMP[0], TEMP[0], SAMP[ADDR[2].x], 2D
  3: MOV OUT[0], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x
i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x
<8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2
x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float,
float, float, float, float, float, i32, float, float) #0 {
main_body:
  %22 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)*
%1, i64 0, i64 0
  %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !0
  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64)
  %25 = bitcast float %24 to i32
  %26 = sext i32 %25 to i64
  %27 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)*
%3, i64 0, i64 %26
  %28 = load <8 x i32>, <8 x i32> addrspace(2)* %27, align 32, !tbaa !0
  %29 = sext i32 %25 to i64
  %30 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)*
%2, i64 0, i64 %29
  %31 = load <4 x i32>, <4 x i32> addrspace(2)* %30, align 16, !tbaa !0
  %32 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32
1061158912, i32 1048576000>, <8 x i32> %28, <4 x i32> %31, i32 15, i32
0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  %33 = extractelement <4 x float> %32, i32 0
  %34 = extractelement <4 x float> %32, i32 1
  %35 = extractelement <4 x float> %32, i32 2
  %36 = extractelement <4 x float> %32, i32 3
  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
  %38 = bitcast i32 %37 to float
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float
%38, float %40, float %38, float %40)
  ret void
}
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