[Mesa-dev] [PATCH 1/5] i965: Push miptree tiling request into flags
Jordan Justen
jordan.l.justen at intel.com
Tue Jul 14 22:19:18 PDT 2015
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
On 2015-07-14 09:56:09, Ben Widawsky wrote:
> With the last few patches a way was provided to influence lower layer miptree
> layout and allocation decisions via flags (replacing bools). For simplicity, I
> chose not to touch the tiling requests because the change was slightly less
> mechanical than replacing the bools.
>
> The goal is to organize the code so we can continue to add new parameters and
> tiling types while minimizing risk to the existing code, and not having to
> constantly add new function parameters.
>
> v2: Rebased on Anuj's recent Yf/Ys changes
> Fix non-msrt MCS allocation (was only happening in gen8 case before)
>
> Cc: Anuj Phogat <anuj.phogat at gmail.com>
> Cc: Chad Versace <chad.versace at intel.com>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 21 ++++++------
> src/mesa/drivers/dri/i965/intel_fbo.c | 6 ++--
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 +++++++++++++-------------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 15 ++++-----
> src/mesa/drivers/dri/i965/intel_tex.c | 2 +-
> src/mesa/drivers/dri/i965/intel_tex_image.c | 3 +-
> src/mesa/drivers/dri/i965/intel_tex_validate.c | 5 +--
> 7 files changed, 50 insertions(+), 47 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 389834f..a12b4af 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -614,8 +614,8 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
> */
> static uint32_t
> brw_miptree_choose_tiling(struct brw_context *brw,
> - enum intel_miptree_tiling_mode requested,
> - const struct intel_mipmap_tree *mt)
> + const struct intel_mipmap_tree *mt,
> + uint32_t layout_flags)
> {
> if (mt->format == MESA_FORMAT_S_UINT8) {
> /* The stencil buffer is W tiled. However, we request from the kernel a
> @@ -624,15 +624,18 @@ brw_miptree_choose_tiling(struct brw_context *brw,
> return I915_TILING_NONE;
> }
>
> + /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
> + assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
> +
> /* Some usages may want only one type of tiling, like depth miptrees (Y
> * tiled), or temporary BOs for uploading data once (linear).
> */
> - switch (requested) {
> - case INTEL_MIPTREE_TILING_ANY:
> + switch (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) {
> + case MIPTREE_LAYOUT_ALLOC_ANY_TILED:
> break;
> - case INTEL_MIPTREE_TILING_Y:
> + case MIPTREE_LAYOUT_ALLOC_YTILED:
> return I915_TILING_Y;
> - case INTEL_MIPTREE_TILING_NONE:
> + case MIPTREE_LAYOUT_ALLOC_LINEAR:
> return I915_TILING_NONE;
> }
>
> @@ -835,7 +838,6 @@ intel_miptree_can_use_tr_mode(const struct intel_mipmap_tree *mt)
> void
> brw_miptree_layout(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> - enum intel_miptree_tiling_mode requested,
> uint32_t layout_flags)
> {
> const unsigned bpp = mt->cpp * 8;
> @@ -852,8 +854,7 @@ brw_miptree_layout(struct brw_context *brw,
> !(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
> !mt->compressed &&
> _mesa_is_format_color_format(mt->format) &&
> - (requested == INTEL_MIPTREE_TILING_Y ||
> - requested == INTEL_MIPTREE_TILING_ANY) &&
> + (layout_flags & MIPTREE_LAYOUT_ALLOC_YTILED) &&
> (bpp && is_power_of_two(bpp)) &&
> /* FIXME: To avoid piglit regressions keep the Yf/Ys tiling
> * disabled at the moment.
> @@ -897,7 +898,7 @@ brw_miptree_layout(struct brw_context *brw,
> if (layout_flags & MIPTREE_LAYOUT_FOR_BO)
> break;
>
> - mt->tiling = brw_miptree_choose_tiling(brw, requested, mt);
> + mt->tiling = brw_miptree_choose_tiling(brw, mt, layout_flags);
> if (is_tr_mode_yf_ys_allowed) {
> if (intel_miptree_can_use_tr_mode(mt))
> break;
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 05e3f8b..26f895b 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -1022,6 +1022,9 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
> struct intel_mipmap_tree *new_mt;
> int width, height, depth;
>
> + uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> + MIPTREE_LAYOUT_ALLOC_ANY_TILED;
> +
> intel_miptree_get_dimensions_for_image(rb->TexImage, &width, &height, &depth);
>
> new_mt = intel_miptree_create(brw, rb->TexImage->TexObject->Target,
> @@ -1030,8 +1033,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
> intel_image->base.Base.Level,
> width, height, depth,
> irb->mt->num_samples,
> - INTEL_MIPTREE_TILING_ANY,
> - MIPTREE_LAYOUT_ACCELERATED_UPLOAD);
> + layout_flags);
>
> if (intel_miptree_wants_hiz_buffer(brw, new_mt)) {
> intel_miptree_alloc_hiz(brw, new_mt);
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index fb896a9..72fba49 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -272,7 +272,6 @@ intel_miptree_create_layout(struct brw_context *brw,
> GLuint height0,
> GLuint depth0,
> GLuint num_samples,
> - enum intel_miptree_tiling_mode requested,
> uint32_t layout_flags)
> {
> struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
> @@ -454,8 +453,10 @@ intel_miptree_create_layout(struct brw_context *brw,
> (brw->has_separate_stencil &&
> intel_miptree_wants_hiz_buffer(brw, mt)))) {
> uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
> - if (brw->gen == 6)
> - stencil_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD;
> + if (brw->gen == 6) {
> + stencil_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD |
> + MIPTREE_LAYOUT_ALLOC_ANY_TILED;
> + }
>
> mt->stencil_mt = intel_miptree_create(brw,
> mt->target,
> @@ -466,7 +467,6 @@ intel_miptree_create_layout(struct brw_context *brw,
> mt->logical_height0,
> mt->logical_depth0,
> num_samples,
> - INTEL_MIPTREE_TILING_ANY,
> stencil_flags);
>
> if (!mt->stencil_mt) {
> @@ -510,7 +510,7 @@ intel_miptree_create_layout(struct brw_context *brw,
> assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
> }
>
> - brw_miptree_layout(brw, mt, requested, layout_flags);
> + brw_miptree_layout(brw, mt, layout_flags);
>
> if (mt->disable_aux_buffers)
> assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
> @@ -616,7 +616,6 @@ intel_miptree_create(struct brw_context *brw,
> GLuint height0,
> GLuint depth0,
> GLuint num_samples,
> - enum intel_miptree_tiling_mode requested_tiling,
> uint32_t layout_flags)
> {
> struct intel_mipmap_tree *mt;
> @@ -634,7 +633,7 @@ intel_miptree_create(struct brw_context *brw,
> mt = intel_miptree_create_layout(brw, target, format,
> first_level, last_level, width0,
> height0, depth0, num_samples,
> - requested_tiling, layout_flags);
> + layout_flags);
> /*
> * pitch == 0 || height == 0 indicates the null texture
> */
> @@ -757,17 +756,15 @@ intel_miptree_create_for_bo(struct brw_context *brw,
>
> target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
>
> - /* 'requested' parameter of intel_miptree_create_layout() is relevant
> - * only for non bo miptree. Tiling for bo is already computed above.
> - * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is
> - * just a place holder and will not make any change to the miptree
> - * tiling format.
> + /* The BO already has a tiling format and we shouldn't confuse the lower
> + * layers by making it try to find a tiling format again.
> */
> + assert((layout_flags &
> + (MIPTREE_LAYOUT_ALLOC_ANY_TILED | MIPTREE_LAYOUT_ALLOC_LINEAR)) == 0);
> layout_flags |= MIPTREE_LAYOUT_FOR_BO;
> mt = intel_miptree_create_layout(brw, target, format,
> 0, 0,
> width, height, depth, 0,
> - INTEL_MIPTREE_TILING_ANY,
> layout_flags);
> if (!mt)
> return NULL;
> @@ -875,11 +872,13 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
> uint32_t depth = 1;
> bool ok;
> GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
> + const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> + MIPTREE_LAYOUT_ALLOC_ANY_TILED;
> +
>
> mt = intel_miptree_create(brw, target, format, 0, 0,
> width, height, depth, num_samples,
> - INTEL_MIPTREE_TILING_ANY,
> - MIPTREE_LAYOUT_ACCELERATED_UPLOAD);
> + layout_flags);
> if (!mt)
> goto fail;
>
> @@ -1384,6 +1383,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> *
> * "The MCS surface must be stored as Tile Y."
> */
> + const uint32_t mcs_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> + MIPTREE_LAYOUT_ALLOC_YTILED;
> mt->mcs_mt = intel_miptree_create(brw,
> mt->target,
> format,
> @@ -1393,8 +1394,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> mt->logical_height0,
> mt->logical_depth0,
> 0 /* num_samples */,
> - INTEL_MIPTREE_TILING_Y,
> - MIPTREE_LAYOUT_ACCELERATED_UPLOAD);
> + mcs_flags);
>
> /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
> *
> @@ -1442,9 +1442,11 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> unsigned mcs_height =
> ALIGN(mt->logical_height0, height_divisor) / height_divisor;
> assert(mt->logical_depth0 == 1);
> - uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
> - if (brw->gen >= 8)
> + uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> + MIPTREE_LAYOUT_ALLOC_YTILED;
> + if (brw->gen >= 8) {
> layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
> + }
> mt->mcs_mt = intel_miptree_create(brw,
> mt->target,
> format,
> @@ -1454,7 +1456,6 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> mcs_height,
> mt->logical_depth0,
> 0 /* num_samples */,
> - INTEL_MIPTREE_TILING_Y,
> layout_flags);
>
> return mt->mcs_mt;
> @@ -1707,6 +1708,7 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
> if (!buf)
> return NULL;
>
> + layout_flags |= MIPTREE_LAYOUT_ALLOC_ANY_TILED;
> buf->mt = intel_miptree_create(brw,
> mt->target,
> mt->format,
> @@ -1716,7 +1718,6 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
> mt->logical_height0,
> mt->logical_depth0,
> mt->num_samples,
> - INTEL_MIPTREE_TILING_ANY,
> layout_flags);
> if (!buf->mt) {
> free(buf);
> @@ -2147,7 +2148,7 @@ intel_miptree_map_blit(struct brw_context *brw,
> map->mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
> 0, 0,
> map->w, map->h, 1,
> - 0, INTEL_MIPTREE_TILING_NONE, 0);
> + 0, 0);
>
> if (!map->mt) {
> fprintf(stderr, "Failed to allocate blit temporary\n");
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index bde6daa..89fdccb 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -516,12 +516,6 @@ struct intel_mipmap_tree
> GLuint refcount;
> };
>
> -enum intel_miptree_tiling_mode {
> - INTEL_MIPTREE_TILING_ANY,
> - INTEL_MIPTREE_TILING_Y,
> - INTEL_MIPTREE_TILING_NONE,
> -};
> -
> void
> intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> @@ -541,8 +535,15 @@ enum {
> MIPTREE_LAYOUT_FOR_BO = 1 << 2,
> MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
> MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
> +
> + MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5,
> + MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6,
> + MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7,
> };
>
> +#define MIPTREE_LAYOUT_ALLOC_ANY_TILED (MIPTREE_LAYOUT_ALLOC_YTILED | \
> + MIPTREE_LAYOUT_ALLOC_XTILED)
> +
> struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
> GLenum target,
> mesa_format format,
> @@ -552,7 +553,6 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
> GLuint height0,
> GLuint depth0,
> GLuint num_samples,
> - enum intel_miptree_tiling_mode,
> uint32_t flags);
>
> struct intel_mipmap_tree *
> @@ -771,7 +771,6 @@ brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
> void
> brw_miptree_layout(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> - enum intel_miptree_tiling_mode requested,
> uint32_t layout_flags);
>
> void *intel_miptree_map_raw(struct brw_context *brw,
> diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
> index b0181ad..8fa5e3c 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex.c
> @@ -145,7 +145,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
> 0, levels - 1,
> width, height, depth,
> num_samples,
> - INTEL_MIPTREE_TILING_ANY, 0);
> + MIPTREE_LAYOUT_ALLOC_ANY_TILED);
>
> if (intel_texobj->mt == NULL) {
> return false;
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
> index e077d5e..226aaeb 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
> @@ -80,8 +80,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
> height,
> depth,
> intelImage->base.Base.NumSamples,
> - INTEL_MIPTREE_TILING_ANY,
> - layout_flags);
> + layout_flags | MIPTREE_LAYOUT_ALLOC_ANY_TILED);
> }
>
> static void
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> index 4991c29..6ebf381 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> @@ -136,6 +136,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
> _mesa_get_format_name(firstImage->base.Base.TexFormat),
> width, height, depth, validate_last_level + 1);
>
> + const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> + MIPTREE_LAYOUT_ALLOC_ANY_TILED;
> intelObj->mt = intel_miptree_create(brw,
> intelObj->base.Target,
> firstImage->base.Base.TexFormat,
> @@ -145,8 +147,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
> height,
> depth,
> 0 /* num_samples */,
> - INTEL_MIPTREE_TILING_ANY,
> - MIPTREE_LAYOUT_ACCELERATED_UPLOAD);
> + layout_flags);
> if (!intelObj->mt)
> return false;
> }
> --
> 2.4.5
>
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