[Mesa-dev] [PATCH v5 3/6] i965: Enable hardware-generated binding tables on render path.

[Abdiel Janulgue]

On 07/17/2015 05:26 AM, Kenneth Graunke wrote:
> On Tuesday, July 07, 2015 11:50:21 AM Abdiel Janulgue wrote:
>> +void
>> +gen7_disable_hw_binding_tables(struct brw_context *brw)
>> +{
>> +   if (!brw->use_resource_streamer)
>> +      return;
>> +
>> +   int pkt_len = brw->gen >= 8 ? 4 : 3;
>> +
>> +   BEGIN_BATCH(pkt_len);
>> +   OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
>> +   if (brw->gen >= 8) {
>> +      OUT_BATCH(0);
>> +      OUT_BATCH(0);
>> +      OUT_BATCH(0);
>> +   } else {
>> +      OUT_BATCH(HSW_BT_POOL_ALLOC_MUST_BE_ONE);
>> +      OUT_BATCH(0);
>> +   }
>> +   ADVANCE_BATCH();
>> +
>> +   /* From the Haswell PRM, Volume 7: 3D Media GPGPU,
>> +    * 3DSTATE_BINDING_TABLE_POOL_ALLOC > Programming Note:
>> +    *
>> +    * "When switching between HW and SW binding table generation, SW must
>> +    * issue a state cache invalidate."
>> +    */
>> +   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
> 
> In the enabling case, Chris mentioned the the flush should go first - does this
> need to be changed, too?  Or is this right, and we should disable in the
> opposite order?  Chris, thoughts?
> 

I guess the flush order needs to be changed here as well. Chris
mentioned this in irc...