[Mesa-dev] [PATCH v2 12/78] i965/nir/vec4: Implement load_const intrinsic

[Jason Ekstrand]

On Thu, Jul 23, 2015 at 3:16 AM, Eduardo Lima Mitev <elima at igalia.com> wrote:
> Similar to fs_nir backend, a nir_local_values map will be filled with
> newly allocated registers as the load_const instrinsic instructions are
> processed. Later, get_nir_src() will fetch the registers from this map
> for sources that are ssa.
> ---
>  src/mesa/drivers/dri/i965/brw_nir.c        |  2 +-
>  src/mesa/drivers/dri/i965/brw_vec4.h       |  1 +
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 19 ++++++++++++++++++-
>  3 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
> index d81d823..a4b65d2 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir.c
> +++ b/src/mesa/drivers/dri/i965/brw_nir.c
> @@ -165,7 +165,7 @@ brw_create_nir(struct brw_context *brw,
>        nir_print_shader(nir, stderr);
>     }
>
> -   nir_convert_from_ssa(nir, true);
> +   nir_convert_from_ssa(nir, is_scalar);
>     nir_validate_shader(nir);
>
>     /* This is the last pass we run before we start emitting stuff.  It
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
> index e0698ee..83ac4c4 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -412,6 +412,7 @@ public:
>                                                const glsl_type *type) = 0;
>
>     dst_reg *nir_locals;
> +   dst_reg *nir_ssa_values;
>     src_reg *nir_inputs;
>     unsigned *nir_uniform_driver_location;
>     dst_reg *nir_system_values;
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index f6b213e..4733b60 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -250,6 +250,8 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl)
>        nir_locals[reg->index] = dst_reg(GRF, alloc.allocate(array_elems));
>     }
>
> +   nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);
> +
>     nir_emit_cf_list(&impl->body);
>  }
>
> @@ -332,7 +334,22 @@ vec4_visitor::nir_emit_instr(nir_instr *instr)
>  void
>  vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
>  {
> -   /* @TODO: Not yet implemented */
> +   dst_reg reg = dst_reg(GRF, alloc.allocate(1));
> +   reg.type =  BRW_REGISTER_TYPE_F;
> +
> +   /* @FIXME: consider emitting vector operations to save some MOVs in
> +    * cases where the components are representable in 8 bits.
> +    * By now, we emit a MOV for each component.
> +    */
> +   for (unsigned i = 0; i < instr->def.num_components; ++i) {
> +      reg.writemask = 1 << i;
> +      emit(MOV(reg, src_reg(instr->value.f[i])));

In the FS, we use integers here.  I don't know that using floats is a
problem, but we should probably be consistent.
--Jason

> +   }
> +
> +   /* Set final writemask */
> +   reg.writemask = brw_writemask_for_size(instr->def.num_components);
> +
> +   nir_ssa_values[instr->def.index] = reg;
>  }
>
>  void
> --
> 2.1.4
>
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