[Mesa-dev] [PATCH 3/5] i965/vec4: Register spilling should never see registers with size != 1

[Iago Toral]

On Fri, 2015-07-24 at 16:20 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga <itoral at igalia.com> writes:
> 
> > Larger registers should have been moved to scratch (like GRF array access)
> > or split to size 1 by the split_virtual_grfs pass.
> 
> Not necessarily.  split_virtual_grfs() won't be able to split stuff
> which is read or written at once by the same instruction -- E.g. by
> send-from-GRF instructions as used for surface messages on e.g.  your
> SSBO implementation.  :)
> 
> We should probably eventually migrate other messages too like the ones
> used for texturing and framebuffer writes to use proper sends from
> GRF...

Okay, in that case I'll include patches to add support for spilling
registers with size > 1 as well.

Thanks,
Iago

> > ---
> >  src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> > index cff5406..80ab813 100644
> > --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> > @@ -271,7 +271,8 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
> >  
> >     for (unsigned i = 0; i < this->alloc.count; i++) {
> >        spill_costs[i] = 0.0;
> > -      no_spill[i] = alloc.sizes[i] != 1;
> > +      no_spill[i] = false;
> > +      assert(this->alloc.sizes[i] == 1);
> >     }
> >  
> >     /* Calculate costs for spilling nodes.  Call it a cost of 1 per
> > -- 
> > 1.9.1
> >
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