[Mesa-dev] [PATCH v2 2/6] i965/vec4: Remove checks for reladdr when checking for spillable registers

[Iago Toral Quiroga]

In theory, GRF array access should have been moved to scratch by the time
we got here, so this should never happen. A full piglit run forcing
spilling of all registers seems to confirm this. The FS backend
does not seem to check for this either.
---
 src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index a9bf0d8..cff5406 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -282,15 +282,13 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
       for (unsigned int i = 0; i < 3; i++) {
 	 if (inst->src[i].file == GRF) {
 	    spill_costs[inst->src[i].reg] += loop_scale;
-            if (inst->src[i].reladdr)
-               no_spill[inst->src[i].reg] = true;
+	    assert(!inst->src[i].reladdr);
 	 }
       }
 
       if (inst->dst.file == GRF) {
 	 spill_costs[inst->dst.reg] += loop_scale;
-         if (inst->dst.reladdr)
-            no_spill[inst->dst.reg] = true;
+	 assert(!inst->dst.reladdr);
       }
 
       switch (inst->opcode) {
-- 
1.9.1