[Mesa-dev] [PATCH] i965: Reserve more batch space to accomodate Gen6 perfmonitors.

[Anuj Phogat]

On Wed, Mar 4, 2015 at 3:46 PM, Kenneth Graunke <kenneth at whitecape.org> wrote:
> Ben noticed that I said each PIPE_CONTROL was 4 DWords, but it's
> actually 5 DWords on Gen6-7.  We've been reserving insufficient space
> for performance monitoring on Sandybridge, which means it would likely
> break if you used that functionality.  (Thankfully, no one does...)
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> We should probably Cc this to stable unless we delete the broken
> performance monitoring code altogether.
>
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
> index 7bdd836..5a16456 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
> @@ -22,12 +22,12 @@ extern "C" {
>   *   - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
>   *   - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
>   *     - Two sets of PIPE_CONTROLs, which become 3 PIPE_CONTROLs each on SNB,
> - *       which are 4 DWords each ==> 2 * 3 * 4 * 4 = 96 bytes
> + *       which are 5 DWords each ==> 2 * 3 * 5 * 4 = 120 bytes
>   *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
>   *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
>   *       Sandybridge PIPE_CONTROL madness.
>   */
> -#define BATCH_RESERVED 146
> +#define BATCH_RESERVED 152
>
>  struct intel_batchbuffer;
>
> --
> 2.2.2
>
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Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>