[Mesa-dev] [PATCH] [v2] i965/skl: Disable partial resolve in VC

[Anuj Phogat]

On Thu, Feb 26, 2015 at 6:14 PM, Ben Widawsky
<benjamin.widawsky at intel.com> wrote:
> Recomendation [sic] is to set this field to 1 always. Programming it to default
> value of 0, may have -ve impact on performance for MSAA WLs.
>
> Another don't suck bit which needs to get set.
>
> Totally untested.
>
> v2: v1 was a mix of two patches. Since 0x7004 is masked, we only need to set it
> once at initialization and make sure the pma workaround doesn't set the mask bit
> (which it doesn't).
> Move LRI to init gpu state (Ken)
> Add a comment.
>
> ... still untested.
>
> Cc: Kenneth Graunke <kenneth at whitecape.org>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 10 ++++++++++
>  src/mesa/drivers/dri/i965/intel_reg.h        |  1 +
>  2 files changed, 11 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 1b84859..c90a34f 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -337,6 +337,16 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
>
>     brw_upload_invariant_state(brw);
>
> +   /* Recommended optimization for Victim Cache eviction in pixel backend. */
> +   if (brw->gen >= 9) {
> +      BEGIN_BATCH(3);
> +      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
> +      OUT_BATCH(GEN7_CACHE_MODE_1);
> +      OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) |
> +                GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
> +      ADVANCE_BATCH();
> +   }
> +
>     if (brw->gen >= 8) {
>        gen8_emit_3dstate_sample_pattern(brw);
>     }
> diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
> index af1c1df..a4bcf3d 100644
> --- a/src/mesa/drivers/dri/i965/intel_reg.h
> +++ b/src/mesa/drivers/dri/i965/intel_reg.h
> @@ -144,5 +144,6 @@
>  #define GEN7_CACHE_MODE_1               0x7004
>  # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
>  # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
> +# define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
>  # define GEN8_HIZ_PMA_MASK_BITS \
>     ((GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16)
> --
> 2.3.1
>
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Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>