[Mesa-dev] [PATCH 6/6] i965/skl: Don't use ALL_SLICES_AT_EACH_LOD

[Ben Widawsky]

On Fri, Feb 20, 2015 at 10:31:08PM +0000, Neil Roberts wrote:
> The render surface state command for Skylake doesn't have the surface
> array spacing bit so I don't think it's possible to select this
> layout. This avoids a kernel panic when running the piglit test below:

Kernel panic!? Please, go on. We cannot cause kernel panics from userspace. It's
a kernel bug if we do.

> 
> ext_framebuffer_multisample-no-color 8 stencil single
> 
> However the test still fails so there may be something else wrong as
> well. The test was not causing a kernel panic before the patch to fix
> the qpitch.
> 
> I think it's also not possible to select this layout on Gen8 so it may
> need to be changed to only be used on Gen7.

I don't think this is the right answer. The array spacing bit goes away because
we can manually specify the qpitch (I think).

We should probably dig into this a bit more. I can help if you'd like.

> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 26 ++++++++++++++++----------
>  1 file changed, 16 insertions(+), 10 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 994670a..018e16b 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -371,19 +371,25 @@ intel_miptree_create_layout(struct brw_context *brw,
>        }
>     }
>  
> -   /* Set array_layout to ALL_SLICES_AT_EACH_LOD when gen7+ array_spacing_lod0
> -    * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces.
> +   /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0
> +    * can be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces
> +    * on Gen 7 and 8.
>      * TODO: can we use it elsewhere?
> +    * TODO: does this actually work on Gen 8?
>      */
> -   switch (mt->msaa_layout) {
> -   case INTEL_MSAA_LAYOUT_NONE:
> -   case INTEL_MSAA_LAYOUT_IMS:
> +   if (brw->gen >= 9) {
>        mt->array_layout = ALL_LOD_IN_EACH_SLICE;
> -      break;
> -   case INTEL_MSAA_LAYOUT_UMS:
> -   case INTEL_MSAA_LAYOUT_CMS:
> -      mt->array_layout = ALL_SLICES_AT_EACH_LOD;
> -      break;
> +   } else {
> +      switch (mt->msaa_layout) {
> +      case INTEL_MSAA_LAYOUT_NONE:
> +      case INTEL_MSAA_LAYOUT_IMS:
> +         mt->array_layout = ALL_LOD_IN_EACH_SLICE;
> +         break;
> +      case INTEL_MSAA_LAYOUT_UMS:
> +      case INTEL_MSAA_LAYOUT_CMS:
> +         mt->array_layout = ALL_SLICES_AT_EACH_LOD;
> +         break;
> +      }
>     }
>  
>     if (target == GL_TEXTURE_CUBE_MAP) {

-- 
Ben Widawsky, Intel Open Source Technology Center