[Mesa-dev] [PATCH v2 4/4] i965/state: Add compute pipeline with empty atom lists

[Jordan Justen]

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h      |  2 ++
 src/mesa/drivers/dri/i965/brw_state.h        |  1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c | 28 +++++++++++++++++++++++++++-
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index e693f50..f15cd7c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -151,6 +151,7 @@ struct brw_wm_prog_data;
 
 enum brw_pipeline {
    BRW_RENDER_PIPELINE,
+   BRW_COMPUTE_PIPELINE,
 
    BRW_NUM_PIPELINES
 };
@@ -1395,6 +1396,7 @@ struct brw_context
 
    int num_atoms[BRW_NUM_PIPELINES];
    const struct brw_tracked_state render_atoms[57];
+   const struct brw_tracked_state compute_atoms[0];
 
    /* If (INTEL_DEBUG & DEBUG_BATCH) */
    struct {
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index ae5ef1f..5e4599d 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -169,6 +169,7 @@ brw_depthbuffer_format(struct brw_context *brw);
  * brw_state.c
  */
 void brw_upload_render_state(struct brw_context *brw);
+void brw_upload_compute_state(struct brw_context *brw);
 void brw_clear_dirty_bits(struct brw_context *brw);
 void brw_init_state(struct brw_context *brw);
 void brw_destroy_state(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 55a9050..0b38c09 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -246,6 +246,10 @@ static const struct brw_tracked_state *gen7_render_atoms[] =
    &haswell_cut_index,
 };
 
+static const struct brw_tracked_state *gen7_compute_atoms[] =
+{
+};
+
 static const struct brw_tracked_state *gen8_render_atoms[] =
 {
    /* Command packets: */
@@ -322,6 +326,10 @@ static const struct brw_tracked_state *gen8_render_atoms[] =
    &gen8_pma_fix,
 };
 
+static const struct brw_tracked_state *gen8_compute_atoms[] =
+{
+};
+
 static void
 brw_upload_initial_gpu_state(struct brw_context *brw)
 {
@@ -349,8 +357,10 @@ brw_get_pipeline_atoms(struct brw_context *brw,
    switch (pipeline) {
    case BRW_RENDER_PIPELINE:
       return &brw->render_atoms[0];
+   case BRW_COMPUTE_PIPELINE:
+      return &brw->compute_atoms[0];
    default:
-      STATIC_ASSERT(BRW_NUM_PIPELINES == 1);
+      STATIC_ASSERT(BRW_NUM_PIPELINES == 2);
       unreachable("Unsupported pipeline");
       return NULL;
    }
@@ -387,6 +397,10 @@ void brw_init_state( struct brw_context *brw )
                  ARRAY_SIZE(brw->render_atoms));
    STATIC_ASSERT(ARRAY_SIZE(gen8_render_atoms) <=
                  ARRAY_SIZE(brw->render_atoms));
+   STATIC_ASSERT(ARRAY_SIZE(gen7_compute_atoms) <=
+                 ARRAY_SIZE(brw->compute_atoms));
+   STATIC_ASSERT(ARRAY_SIZE(gen8_compute_atoms) <=
+                 ARRAY_SIZE(brw->compute_atoms));
 
    brw_init_caches(brw);
 
@@ -394,10 +408,16 @@ void brw_init_state( struct brw_context *brw )
       brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
                               gen8_render_atoms,
                               ARRAY_SIZE(gen8_render_atoms));
+      brw_copy_pipeline_atoms(brw, BRW_COMPUTE_PIPELINE,
+                              gen8_compute_atoms,
+                              ARRAY_SIZE(gen8_compute_atoms));
    } else if (brw->gen == 7) {
       brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
                               gen7_render_atoms,
                               ARRAY_SIZE(gen7_render_atoms));
+      brw_copy_pipeline_atoms(brw, BRW_COMPUTE_PIPELINE,
+                              gen7_compute_atoms,
+                              ARRAY_SIZE(gen7_compute_atoms));
    } else if (brw->gen == 6) {
       brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
                               gen6_atoms, ARRAY_SIZE(gen6_atoms));
@@ -734,3 +754,9 @@ brw_clear_dirty_bits(struct brw_context *brw)
    struct brw_state_flags *state = &brw->state.dirty;
    memset(state, 0, sizeof(*state));
 }
+
+void
+brw_upload_compute_state(struct brw_context *brw)
+{
+   brw_upload_pipeline_state(brw, BRW_COMPUTE_PIPELINE);
+}
-- 
2.1.4