[Mesa-dev] [PATCH] i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN6

[Marius Predut]

On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-aliasing algorithm give up - garbage line is generated.
Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” (one-pixel-wide), non-antialiased lines.
Lines rendered with zero Line Width are rasterized using Grid Intersection Quantization rules as specified by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832
Signed-off-by: Marius Predut <marius.predut at intel.com>
---
 src/mesa/drivers/dri/i965/gen6_sf_state.c |   12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index f9d8d27..1bed444 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -367,9 +367,15 @@ upload_sf_state(struct brw_context *brw)
       float line_width =
          roundf(CLAMP(ctx->Line.Width, 0.0, ctx->Const.MaxLineWidth));
       uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
-      /* TODO: line width of 0 is not allowed when MSAA enabled */
-      if (line_width_u3_7 == 0)
-         line_width_u3_7 = 1;
+
+      if (!(multisampled_fbo && ctx->Multisample.Enabled)) {
+        if (ctx->Line.SmoothFlag && ctx->Line.Width <=1)
+              line_width_u3_7 = 0;
+      } else {
+            if (line_width_u3_7 == 0)
+                line_width_u3_7 = 1;
+      }
+
       dw3 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
    }
    if (ctx->Line.SmoothFlag) {
-- 
1.7.9.5