[Mesa-dev] [PATCH 1/5] glsl: Allow vector logic ops to be generated.
Matt Turner
mattst88 at gmail.com
Wed Mar 18 11:37:45 PDT 2015
They're not accessible from the source language, but optimizations are
allowed to generate them.
---
src/glsl/ir_validate.cpp | 6 +++---
src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 9 +++------
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 7a7688c..72c5f06 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -543,9 +543,9 @@ ir_validate::visit_leave(ir_expression *ir)
case ir_binop_logic_and:
case ir_binop_logic_xor:
case ir_binop_logic_or:
- assert(ir->type == glsl_type::bool_type);
- assert(ir->operands[0]->type == glsl_type::bool_type);
- assert(ir->operands[1]->type == glsl_type::bool_type);
+ assert(ir->type->base_type == GLSL_TYPE_BOOL);
+ assert(ir->operands[0]->type->base_type == GLSL_TYPE_BOOL);
+ assert(ir->operands[1]->type->base_type == GLSL_TYPE_BOOL);
break;
case ir_binop_dot:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 933fdde..4049b09 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -271,6 +271,9 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
case ir_binop_bit_and:
case ir_binop_bit_xor:
case ir_binop_bit_or:
+ case ir_binop_logic_and:
+ case ir_binop_logic_xor:
+ case ir_binop_logic_or:
case ir_binop_less:
case ir_binop_greater:
case ir_binop_lequal:
@@ -329,12 +332,6 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
break;
}
- case ir_binop_logic_and:
- case ir_binop_logic_xor:
- case ir_binop_logic_or:
- ir->fprint(stderr);
- fprintf(stderr, "\n");
- unreachable("not reached: expression operates on scalars only");
case ir_binop_all_equal:
case ir_binop_any_nequal: {
ir_expression *last = NULL;
--
2.0.5
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