[Mesa-dev] [PATCH 01/23] i965/fs: Refactor out guts of fs_visitor::try_opt_frontfacing_ternary
Ian Romanick
idr at freedesktop.org
Fri Mar 20 13:58:01 PDT 2015
From: Ian Romanick <ian.d.romanick at intel.com>
The next patch will add a second user.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue at intel.com>
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 105 +++++++++++++++------------
1 file changed, 57 insertions(+), 48 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 60a7a97..3388098 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2800,6 +2800,62 @@ fs_visitor::emit_if_gen6(ir_if *ir)
emit(IF(this->result, fs_reg(0), BRW_CONDITIONAL_NZ));
}
+static void
+emit_frontfacing_to_float_one_neg_one(fs_visitor *v,
+ const fs_reg &dst,
+ ir_constant *then_rhs,
+ ir_constant *else_rhs)
+{
+ fs_reg tmp = v->vgrf(glsl_type::int_type);
+ if (v->brw->gen >= 6) {
+ /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
+ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g0.negate = true;
+ }
+
+ tmp.type = BRW_REGISTER_TYPE_W;
+ tmp.subreg_offset = 2;
+ tmp.stride = 2;
+
+ fs_inst *or_inst = v->emit(v->OR(tmp, g0, fs_reg(0x3f80)));
+ or_inst->src[1].type = BRW_REGISTER_TYPE_UW;
+
+ tmp.type = BRW_REGISTER_TYPE_D;
+ tmp.subreg_offset = 0;
+ tmp.stride = 1;
+ } else {
+ /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
+ fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g1_6.negate = true;
+ }
+
+ v->emit(v->OR(tmp, g1_6, fs_reg(0x3f800000)));
+ }
+ v->emit(v->AND(dst, tmp, fs_reg(0xbf800000)));
+}
+
bool
fs_visitor::try_opt_frontfacing_ternary(ir_if *ir)
{
@@ -2836,55 +2892,8 @@ fs_visitor::try_opt_frontfacing_ternary(ir_if *ir)
then_assign->lhs->accept(this);
fs_reg dst = this->result;
dst.type = BRW_REGISTER_TYPE_D;
- fs_reg tmp = vgrf(glsl_type::int_type);
-
- if (brw->gen >= 6) {
- /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
- fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
-
- /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
- *
- * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
- * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
- *
- * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
- */
-
- if (then_rhs->is_negative_one()) {
- assert(else_rhs->is_one());
- g0.negate = true;
- }
-
- tmp.type = BRW_REGISTER_TYPE_W;
- tmp.subreg_offset = 2;
- tmp.stride = 2;
- fs_inst *or_inst = emit(OR(tmp, g0, fs_reg(0x3f80)));
- or_inst->src[1].type = BRW_REGISTER_TYPE_UW;
-
- tmp.type = BRW_REGISTER_TYPE_D;
- tmp.subreg_offset = 0;
- tmp.stride = 1;
- } else {
- /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
- fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
-
- /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
- *
- * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
- * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
- *
- * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
- */
-
- if (then_rhs->is_negative_one()) {
- assert(else_rhs->is_one());
- g1_6.negate = true;
- }
-
- emit(OR(tmp, g1_6, fs_reg(0x3f800000)));
- }
- emit(AND(dst, tmp, fs_reg(0xbf800000)));
+ emit_frontfacing_to_float_one_neg_one(this, dst, then_rhs, else_rhs);
return true;
}
--
2.1.0
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