[Mesa-dev] [PATCH 5/6] i965: Attempt to blit for larger textures

[Neil Roberts]

Ben Widawsky <benjamin.widawsky at intel.com> writes:

> diff --git a/src/mesa/drivers/dri/i965/intel_blit.h b/src/mesa/drivers/dri/i965/intel_blit.h
> index 52dd67c..aff2d58 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.h
> +++ b/src/mesa/drivers/dri/i965/intel_blit.h
> @@ -78,14 +78,34 @@ void intel_emit_linear_blit(struct brw_context *brw,
>  			    unsigned int src_offset,
>  			    unsigned int size);
>  
> +
> +/* Returns the height of the tiling format. This would be measured in scanlines
> + * (of pitch bytes)
> + */
> +static inline uint32_t
> +intel_blit_tile_height(uint32_t tiling)
> +{
> +   const long PAGE_SIZE = sysconf(_SC_PAGE_SIZE);
> +   switch (tiling) {
> +   case I915_TILING_X:
> +      return PAGE_SIZE / 512;
> +   case I915_TILING_Y:
> +      return PAGE_SIZE / 128;
> +   case I915_TILING_NONE:
> +      return 1;
> +   default:
> +      unreachable("Unknown tiling format\n");
> +   }
> +}
> +

It seems a bit odd to base this on the page size. I guess it is correct
because the tile size is chosen to be 4K to match the page size.
However, other places in Mesa just treat these as constants. For
example, look at the top of intel_tiled_memcpy.c. Maybe it would be
better to move those constants to a shared header somewhere?

>  static inline uint32_t
> -intel_blit_max_height(void)
> +intel_blit_max_height(uint32_t tiling)
>  {
>     /* The docs say that the blitter is capable of transferring 65536 scanlines
>      * per blit, however the commands we use only have a signed 16b value thus
>      * making the practical limit 15b.
>      */
> -   return INTEL_MAX_BLIT_ROWS;
> +   return INTEL_MAX_BLIT_ROWS - intel_blit_tile_height(tiling);
>  }

Can you explain this hunk? Maybe it could do with a comment because at
least I don't understand why you are subtracting the tile height here.

- Neil