[Mesa-dev] [PATCH 12/13] i965: Add typed surface access opcodes.
currojerez at riseup.net
Mon May 4 04:20:57 PDT 2015
"Pohjolainen, Topi" <topi.pohjolainen at intel.com> writes:
> Unfortunately mail server has purged the original patch number 13. I took
> a look instead in your recent image-load-store-nir branch.
You probably meant the image-load-store-scalar branch?
> I studied the fence mechanism a little in bspec, and based on that I
> can't see anything obvious amiss. Small nit below but:
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> Sorry for dropping the ball for such a long time.
> +brw_memory_fence(struct brw_codegen *p,
> + struct brw_reg dst)
> + const struct brw_device_info *devinfo = p->devinfo;
> + const bool commit_enable = (devinfo->gen == 7 && !devinfo->is_haswell);
> You can drop the extra ().
Thank you Topi, I've fixed that locally.
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