[Mesa-dev] [v2 09/12] i965: Pass texture target as parameter for surface setup
Topi Pohjolainen
topi.pohjolainen at intel.com
Wed May 6 04:25:15 PDT 2015
Also changed a couple of direct shifts into SET_FIELD().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++++++------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 11 +++++------
src/mesa/drivers/dri/i965/gen8_surface_state.c | 13 +++++--------
4 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 81878d9..5d853d5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -986,7 +986,7 @@ struct brw_context
void (*update_texture_surface)(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
- uint32_t effective_depth,
+ GLenum target, uint32_t effective_depth,
uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0bb5621..84f4aa5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -310,7 +310,7 @@ update_buffer_texture_surface(struct gl_context *ctx,
static void
brw_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
+ struct gl_texture_object *tObj, GLenum target,
uint32_t effective_depth /* unused */,
uint32_t tex_format, int swizzle /* unused */,
uint32_t *surf_offset,
@@ -351,10 +351,10 @@ brw_update_texture_surface(struct brw_context *brw,
}
}
- surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
- BRW_SURFACE_CUBEFACE_ENABLES |
- tex_format << BRW_SURFACE_FORMAT_SHIFT);
+ surf[0] = SET_FIELD(translate_tex_target(target), BRW_SURFACE_TYPE) |
+ BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
+ BRW_SURFACE_CUBEFACE_ENABLES |
+ tex_format << BRW_SURFACE_FORMAT_SHIFT;
surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
@@ -831,7 +831,7 @@ update_texture_surface(struct gl_context *ctx,
uint32_t effective_depth = (tObj->Immutable && tObj->Target != GL_TEXTURE_3D)
? tObj->NumLayers : mt->logical_depth0;
- brw->vtbl.update_texture_surface(brw, mt, tObj,
+ brw->vtbl.update_texture_surface(brw, mt, tObj, tObj->Target,
effective_depth, tex_format,
swizzle, surf_offset, for_gather);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index b5cb976..0769ab8 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -267,7 +267,7 @@ static void
gen7_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
- uint32_t effective_depth,
+ GLenum target, uint32_t effective_depth,
uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather)
@@ -281,12 +281,12 @@ gen7_update_texture_surface(struct brw_context *brw,
if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
- surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- tex_format << BRW_SURFACE_FORMAT_SHIFT |
+ surf[0] = SET_FIELD(translate_tex_target(target), BRW_SURFACE_TYPE) |
+ SET_FIELD(tex_format, BRW_SURFACE_FORMAT) |
gen7_surface_tiling_mode(mt->tiling);
/* mask of faces present in cube map; for other surfaces MBZ. */
- if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
+ if (target == GL_TEXTURE_CUBE_MAP || target == GL_TEXTURE_CUBE_MAP_ARRAY)
surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
if (mt->align_h == 4)
@@ -294,8 +294,7 @@ gen7_update_texture_surface(struct brw_context *brw,
if (mt->align_w == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- if (_mesa_is_array_texture(tObj->Target) ||
- tObj->Target == GL_TEXTURE_CUBE_MAP)
+ if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
surf[0] |= GEN7_SURFACE_IS_ARRAY;
if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index e4c06b6..fa8a5e6 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -153,7 +153,7 @@ static void
gen8_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
struct gl_texture_object *tObj,
- uint32_t effective_depth,
+ GLenum target, uint32_t effective_depth,
uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather)
@@ -179,19 +179,16 @@ gen8_update_texture_surface(struct brw_context *brw,
uint32_t *surf = allocate_surface_state(brw, surf_offset);
- surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
- tex_format << BRW_SURFACE_FORMAT_SHIFT |
+ surf[0] = SET_FIELD(translate_tex_target(target), BRW_SURFACE_TYPE) |
+ SET_FIELD(tex_format, BRW_SURFACE_FORMAT) |
vertical_alignment(mt) |
horizontal_alignment(mt) |
tiling_mode;
- if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
- tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ if (target == GL_TEXTURE_CUBE_MAP || target == GL_TEXTURE_CUBE_MAP_ARRAY)
surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
- }
- if (_mesa_is_array_texture(tObj->Target) ||
- tObj->Target == GL_TEXTURE_CUBE_MAP)
+ if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
surf[0] |= GEN8_SURFACE_IS_ARRAY;
surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
--
1.9.3
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