[Mesa-dev] [PATCH 7/8] [v3] i965: Add renderbuffer surface indexes to debug
Ben Widawsky
ben at bwidawsk.net
Mon May 18 10:40:10 PDT 2015
On Mon, May 18, 2015 at 11:26:47AM +0300, Pohjolainen, Topi wrote:
> On Fri, May 15, 2015 at 10:06:23PM -0700, Ben Widawsky wrote:
> > This patch is optional in the series. It does make the output much cleaner, but
> > there is some risk.
>
> What is the risk, I couldn't figure it out myself. To me the patch make sense
> and it would have been useful for me before in more than occasion.
All the other patches in the series on enable code when INTEL_DEBUG=batch is
turned on. This patch however acts upon all batches which use a surface. Since I
was initially proposing to just merge what I wrote and fix it as needed, I was
giving people a chance to say, "Acked-by all but patch 7, where I need to go
review it."
In either event, I think it turned out fine if people actually looked at it.
>
> >
> > Sample output (v3):
> > 0x00007e80: 0x231d7000: SURF000: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4 Y-tiled
> > 0x00007e84: 0x05000000: SURF000: MOCS: 0x5 Base MIP: 0.0 (0 mips) Surface QPitch: 0
> > 0x00007e88: 0x009f009f: SURF000: 160x160 [AUX_NONE]
> > 0x00007e8c: 0x0000027f: SURF000: 1 slices (depth), pitch: 640
> > 0x00007e90: 0x00000000: SURF000: min array element: 0, array extent 1, MULTISAMPLE_1
> > 0x00007e94: 0x00000000: SURF000: x,y offset: 0,0, min LOD: 0
> > 0x00007e98: 0x00000000: SURF000: AUX pitch: 0 qpitch: 0
> > 0x00007e9c: 0x09770000: SURF000: Clear color: R(0)G(0)B(0)A(0)
> > 0x00007ea0: 0x00001000: SURF000: 0x00001000
> > 0x00007ea4: 0x00000000: SURF000: 0x00000000
> > 0x00007ea8: 0x00000000: SURF000: 0x00000000
> > 0x00007eac: 0x00000000: SURF000: 0x00000000
> > 0x00007e40: 0x234df000: SURF001: 2D R11G11B10_FLOAT VALIGN4 HALIGN16 Y-tiled
> > 0x00007e44: 0x09000000: SURF001: MOCS: 0x9 Base MIP: 0.0 (0 mips) Surface QPitch: 0
> > 0x00007e48: 0x009f009f: SURF001: 160x160 [AUX_CCS_D (Uncompressed, MULTISAMPLE_COUNT=1)]
> > 0x00007e4c: 0x0000027f: SURF001: 1 slices (depth), pitch: 640
> > 0x00007e50: 0x00000000: SURF001: min array element: 0, array extent 1, MULTISAMPLE_1
> > 0x00007e54: 0x00000000: SURF001: x,y offset: 0,0, min LOD: 0
> > 0x00007e58: 0x00000001: SURF001: AUX pitch: 0 qpitch: 0
> > 0x00007e5c: 0x09770000: SURF001: Clear color: R(0)G(0)B(0)A(0)
> > 0x00007e60: 0x0002b000: SURF001: 0x0002b000
> > 0x00007e64: 0x00000000: SURF001: 0x00000000
> > 0x00007e68: 0x0002a000: SURF001: 0x0002a000
> > 0x00007e6c: 0x00000000: SURF001: 0x00000000
> >
> > v2: Rebased on Topi's recent series which changed around some of the gen8
> > surface setup code.
> >
> > v3: Use ralloc_asprintf instead of asprintf to be more friendly to non-GNU
> > platforms.
> >
> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > ---
> > src/mesa/drivers/dri/i965/brw_context.h | 1 +
> > src/mesa/drivers/dri/i965/brw_state.h | 13 ++++++++-----
> > src/mesa/drivers/dri/i965/brw_state_batch.c | 20 ++++++++++++--------
> > src/mesa/drivers/dri/i965/brw_state_dump.c | 12 ++++++++----
> > src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 ++++++++-------
> > 5 files changed, 37 insertions(+), 24 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
> > index 49f5269..bb5d41d 100644
> > --- a/src/mesa/drivers/dri/i965/brw_context.h
> > +++ b/src/mesa/drivers/dri/i965/brw_context.h
> > @@ -1466,6 +1466,7 @@ struct brw_context
> > uint32_t offset;
> > uint32_t size;
> > enum aub_state_struct_type type;
> > + int index;
> > } *state_batch_list;
> > int state_batch_count;
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
> > index 26fdae6..df694c9 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state.h
> > +++ b/src/mesa/drivers/dri/i965/brw_state.h
> > @@ -229,11 +229,14 @@ void brw_destroy_caches( struct brw_context *brw );
> > #define BRW_BATCH_STRUCT(brw, s) \
> > intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
> >
> > -void *brw_state_batch(struct brw_context *brw,
> > - enum aub_state_struct_type type,
> > - int size,
> > - int alignment,
> > - uint32_t *out_offset);
> > +void *__brw_state_batch(struct brw_context *brw,
> > + enum aub_state_struct_type type,
> > + int size,
> > + int alignment,
> > + int index,
> > + uint32_t *out_offset);
> > +#define brw_state_batch(brw, type, size, alignment, out_offset) \
> > + __brw_state_batch(brw, type, size, alignment, 0, out_offset)
> >
> > /* brw_wm_surface_state.c */
> > void gen4_init_vtable_surface_functions(struct brw_context *brw);
> > diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
> > index 45dca69..a405a80 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state_batch.c
> > +++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
> > @@ -38,7 +38,8 @@ static void
> > brw_track_state_batch(struct brw_context *brw,
> > enum aub_state_struct_type type,
> > uint32_t offset,
> > - int size)
> > + int size,
> > + int index)
> > {
> > struct intel_batchbuffer *batch = &brw->batch;
> >
> > @@ -53,6 +54,7 @@ brw_track_state_batch(struct brw_context *brw,
> > brw->state_batch_list[brw->state_batch_count].offset = offset;
> > brw->state_batch_list[brw->state_batch_count].size = size;
> > brw->state_batch_list[brw->state_batch_count].type = type;
> > + brw->state_batch_list[brw->state_batch_count].index = index;
> > brw->state_batch_count++;
> > }
> >
> > @@ -108,18 +110,20 @@ brw_annotate_aub(struct brw_context *brw)
> > * margin (4096 bytes, even if the object is just a 20-byte surface
> > * state), and more buffers to walk and count for aperture size checking.
> > *
> > - * However, due to the restrictions inposed by the aperture size
> > + * However, due to the restrictions imposed by the aperture size
> > * checking performance hacks, we can't have the batch point at a
> > * separate indirect state buffer, because once the batch points at
> > * it, no more relocations can be added to it. So, we sneak these
> > * buffers in at the top of the batchbuffer.
> > */
> > void *
> > -brw_state_batch(struct brw_context *brw,
> > - enum aub_state_struct_type type,
> > - int size,
> > - int alignment,
> > - uint32_t *out_offset)
> > +__brw_state_batch(struct brw_context *brw,
> > + enum aub_state_struct_type type,
> > + int size,
> > + int alignment,
> > + int index,
> > + uint32_t *out_offset)
> > +
> > {
> > struct intel_batchbuffer *batch = &brw->batch;
> > uint32_t offset;
> > @@ -140,7 +144,7 @@ brw_state_batch(struct brw_context *brw,
> > batch->state_batch_offset = offset;
> >
> > if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_AUB)))
> > - brw_track_state_batch(brw, type, offset, size);
> > + brw_track_state_batch(brw, type, offset, size, index);
> >
> > *out_offset = offset;
> > return batch->map + (offset>>2);
> > diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c
> > index 232d0c1..b3460c4 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state_dump.c
> > +++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
> > @@ -259,12 +259,13 @@ static float q_to_float(uint32_t data, int integer_end, int integer_start,
> > return n * exp2(-(fractional_end - fractional_start + 1));
> > }
> >
> > -static void dump_gen8_surface_state(struct brw_context *brw, uint32_t offset)
> > +static void
> > +dump_gen8_surface_state(struct brw_context *brw, uint32_t offset, int index)
> > {
> > - const char *name = "SURF";
> > uint32_t *surf = brw->batch.bo->virtual + offset;
> > int aux_mode = surf[6] & INTEL_MASK(2, 0);
> > const char *aux_str;
> > + char *name;
> >
> > if (brw->gen >= 9 && (aux_mode == 1 || aux_mode == 5)) {
> > bool msrt = GET_BITS(surf[4], 5, 3) > 0;
> > @@ -280,7 +281,8 @@ static void dump_gen8_surface_state(struct brw_context *brw, uint32_t offset)
> > aux_str = ralloc_asprintf(NULL, "%s", surface_aux_mode[aux_mode]);
> > }
> >
> > - batch_out(brw, "SURF'", offset, 0, "%s %s %s VALIGN%d HALIGN%d %s\n",
> > + name = ralloc_asprintf(NULL, "SURF%03d", index);
> > + batch_out(brw, name, offset, 0, "%s %s %s VALIGN%d HALIGN%d %s\n",
> > get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
> > get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)),
> > (surf[0] & GEN7_SURFACE_IS_ARRAY) ? "array" : "",
> > @@ -325,6 +327,7 @@ static void dump_gen8_surface_state(struct brw_context *brw, uint32_t offset)
> > batch_out(brw, name, offset, i, "0x%08x\n", surf[i]);
> >
> > ralloc_free((void *)aux_str);
> > + ralloc_free(name);
> > }
> >
> > static void
> > @@ -713,7 +716,8 @@ dump_state_batch(struct brw_context *brw)
> > break;
> > case AUB_TRACE_SURFACE_STATE:
> > if (brw->gen >= 8) {
> > - dump_gen8_surface_state(brw, offset);
> > + dump_gen8_surface_state(brw, offset,
> > + brw->state_batch_list[i].index);
> > } else if (brw->gen >= 7) {
> > dump_gen7_surface_state(brw, offset);
> > } else {
> > diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> > index d0c2d80..672fc70 100644
> > --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> > @@ -100,11 +100,11 @@ horizontal_alignment(const struct intel_mipmap_tree *mt)
> > }
> >
> > static uint32_t *
> > -allocate_surface_state(struct brw_context *brw, uint32_t *out_offset)
> > +allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index)
> > {
> > int dwords = brw->gen >= 9 ? 16 : 13;
> > - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
> > - dwords * 4, 64, out_offset);
> > + uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
> > + dwords * 4, 64, index, out_offset);
> > memset(surf, 0, dwords * 4);
> > return surf;
> > }
> > @@ -120,7 +120,7 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
> > bool rw)
> > {
> > const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
> > - uint32_t *surf = allocate_surface_state(brw, out_offset);
> > + uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
> >
> > surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
> > surface_format << BRW_SURFACE_FORMAT_SHIFT |
> > @@ -164,6 +164,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
> > struct intel_mipmap_tree *aux_mt = NULL;
> > uint32_t aux_mode = 0;
> > uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
> > + int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
> > unsigned tiling_mode, pitch;
> >
> > if (mt->format == MESA_FORMAT_S_UINT8) {
> > @@ -179,7 +180,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
> > aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
> > }
> >
> > - uint32_t *surf = allocate_surface_state(brw, surf_offset);
> > + uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
> >
> > surf[0] = translate_tex_target(target) << BRW_SURFACE_TYPE_SHIFT |
> > format << BRW_SURFACE_FORMAT_SHIFT |
> > @@ -310,7 +311,7 @@ gen8_emit_null_surface_state(struct brw_context *brw,
> > unsigned samples,
> > uint32_t *out_offset)
> > {
> > - uint32_t *surf = allocate_surface_state(brw, out_offset);
> > + uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
> >
> > surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
> > BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
> > @@ -392,7 +393,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
> > aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
> > }
> >
> > - uint32_t *surf = allocate_surface_state(brw, &offset);
> > + uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
> >
> > surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
> > (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
> > --
> > 2.4.1
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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