[Mesa-dev] [PATCH] i965: Use padding requirement cube map array type

Ben Widawsky benjamin.widawsky at intel.com
Mon May 18 12:05:28 PDT 2015

"The value of j is still equal to q for mip level alignment and QPitch
calculation. For cube surfaces, an additional two rows of padding are required
at the bottom of the surface...  This is due to the potential rotation of cache
line orientation from memory to cache." "

Cube map array applies as a cube surface.

It's not well understood why this is needed, but it seems like it is.  No
changes in piglit (the g45 results are invalid).

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
 src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 72b02a2..ea7740a 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -344,7 +344,8 @@ align_cube(struct intel_mipmap_tree *mt)
     * memory.  As a result, the docs say in Surface Padding Requirements:
     * Sampling Engine Surfaces that two extra rows of padding are required.
-   if (mt->target == GL_TEXTURE_CUBE_MAP)
+   if (mt->target == GL_TEXTURE_CUBE_MAP ||
+       mt->target == GL_TEXTURE_CUBE_MAP_ARRAY)
       mt->total_height += 2;

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