[Mesa-dev] [PATCH 1/5] i965: Define HW-binding table and resource streamer control opcodes

[Pohjolainen, Topi]

On Wed, May 20, 2015 at 09:32:06AM +0300, Abdiel Janulgue wrote:
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h | 24 ++++++++++++++++++++++++
>  src/mesa/drivers/dri/i965/intel_reg.h   |  3 +++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> index dedc381..f151df1 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1618,6 +1618,30 @@ enum brw_message_target {
>  #define _3DSTATE_BINDING_TABLE_POINTERS_GS	0x7829 /* GEN7+ */
>  #define _3DSTATE_BINDING_TABLE_POINTERS_PS	0x782A /* GEN7+ */
>  
> +#define _3DSTATE_BINDING_TABLE_POOL_ALLOC       0x7919 /* GEN7.5+ */
> +#define BRW_HW_BINDING_TABLE_ENABLE_SHIFT       11     /* GEN7.5+ */
> +#define BRW_HW_BINDING_TABLE_ENABLE_MASK        INTEL_MASK(11, 11)
> +#define BRW_HW_BINDING_TABLE_ON                 1
> +#define BRW_HW_BINDING_TABLE_OFF                0

Could you explain why you chose not to use the simpler form I suggested?

   #define BRW_HW_BINDING_TABLE_ENABLE             (1 << 11)

> +#define GEN7_HW_BT_MOCS_SHIFT                   7
> +#define GEN7_HW_BT_MOCS_MASK                    INTEL_MASK(10, 7)
> +#define GEN8_HW_BT_MOCS_SHIFT                   0
> +#define GEN8_HW_BT_MOCS_MASK                    INTEL_MASK(6, 0)
> +/* Only required in HSW */
> +#define HSW_HW_BINDING_TABLE_RESERVED           (3 << 5)
> +
> +#define _3DSTATE_BINDING_TABLE_EDIT_VS          0x7843 /* GEN7.5 */
> +#define _3DSTATE_BINDING_TABLE_EDIT_GS          0x7844 /* GEN7.5 */
> +#define _3DSTATE_BINDING_TABLE_EDIT_HS          0x7845 /* GEN7.5 */
> +#define _3DSTATE_BINDING_TABLE_EDIT_DS          0x7846 /* GEN7.5 */
> +#define _3DSTATE_BINDING_TABLE_EDIT_PS          0x7847 /* GEN7.5 */
> +#define BRW_BINDING_TABLE_INDEX_SHIFT           16
> +#define BRW_BINDING_TABLE_INDEX_MASK            INTEL_MASK(23, 16)
> +
> +#define BRW_BINDING_TABLE_EDIT_TARGET_ALL       3
> +#define BRW_BINDING_TABLE_EDIT_TARGET_CORE1     2
> +#define BRW_BINDING_TABLE_EDIT_TARGET_CORE0     1
> +
>  #define _3DSTATE_SAMPLER_STATE_POINTERS		0x7802 /* GEN6+ */
>  # define PS_SAMPLER_STATE_CHANGE				(1 << 12)
>  # define GS_SAMPLER_STATE_CHANGE				(1 << 9)
> diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
> index bd14e18..98adf45 100644
> --- a/src/mesa/drivers/dri/i965/intel_reg.h
> +++ b/src/mesa/drivers/dri/i965/intel_reg.h
> @@ -47,6 +47,9 @@
>  /* Load a value from memory into a register.  Only available on Gen7+. */
>  #define GEN7_MI_LOAD_REGISTER_MEM	(CMD_MI | (0x29 << 23))
>  # define MI_LOAD_REGISTER_MEM_USE_GGTT		(1 << 22)
> +/* Haswell RS control */
> +#define MI_RS_CONTROL                   (CMD_MI | (0x6 << 23))
> +#define MI_RS_STORE_DATA_IMM            (CMD_MI | (0x2b << 23))
>  
>  /* Manipulate the predicate bit based on some register values. Only on Gen7+ */
>  #define GEN7_MI_PREDICATE		(CMD_MI | (0xC << 23))
> -- 
> 1.9.1
> 
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