[Mesa-dev] [PATCH 0/6] Begin reworking mipmap tree layout + HALIGN fixes gen8+

[Ben Widawsky]

Initially I wanted to just fix our boats HALIGN code for mcs surfaces on gen8+
(the 5th patch in the series). However, I soon realized why the original
implementation was wrong... the mipmap tree layout/creation is very entangled.

This patch series' primary purpose is to fix the HALIGN constraints for gen8+,
but it begins to rework the mipmap tree code (patch 1, and 3). I have more
patches which further clean things up, but as they do not actually fix anything,
I'll work on them and send them later/separately.

We have data that this fixes some number of hangs (not all) on SKL
(https://bugs.freedesktop.org/show_bug.cgi?id=90561). I don't remember seeing
any fixes on BDW, but I do know reverting Anuj's original implementation does
nothing to piglit either.

Cc: Anuj Phogat <anuj.phogat at intel.com>
Cc: Jordan Justen <jljusten at gmail.com>

Ben Widawsky (6):
  i965: Consolidate certain miptree params to flags
  i965/gen9: Only allow Y-Tiled MCS buffers
  i965: Extract tiling from fast clear decision
  i965/gen8: Correct HALIGN for AUX surfaces
  i965/gen9: Set HALIGN_16 for all aux buffers
  i965/gen8+: Add aux buffer alignment assertions

 src/mesa/drivers/dri/i965/brw_tex_layout.c     |  16 +--
 src/mesa/drivers/dri/i965/gen8_surface_state.c |   4 +
 src/mesa/drivers/dri/i965/intel_fbo.c          |   5 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c  | 137 +++++++++++++++----------
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h  |  24 +++--
 src/mesa/drivers/dri/i965/intel_pixel_draw.c   |   2 +-
 src/mesa/drivers/dri/i965/intel_tex.c          |   8 +-
 src/mesa/drivers/dri/i965/intel_tex.h          |   2 +-
 src/mesa/drivers/dri/i965/intel_tex_image.c    |  14 ++-
 src/mesa/drivers/dri/i965/intel_tex_validate.c |   3 +-
 10 files changed, 127 insertions(+), 88 deletions(-)

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2.4.2