[Mesa-dev] [PATCH 4/6] i965/gen8: Correct HALIGN for AUX surfaces
Pohjolainen, Topi
topi.pohjolainen at intel.com
Thu May 28 23:46:34 PDT 2015
On Thu, May 28, 2015 at 10:21:32AM -0700, Ben Widawsky wrote:
> This restriction was attempted in this commit:
> commit 47053464630888f819ef8cc44278f1a1220159b9
> Author: Anuj Phogat <anuj.phogat at gmail.com>
> Date: Fri Feb 13 11:21:21 2015 -0800
>
> i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT
>
> However, the commit itself doesn't achieve the desired goal as determined by the
> asserts which the next patch adds. mcs_mt is never a value because we're in the
> process of allocating the mcs_mt miptree when we get to this function. I didn't
> check, but perhaps this would work with blorp, however, meta clears allocate the
> miptree structure (which AFAICT needs the alignment also) way before it
> allocates using meta clears where the renderbuffer is allocated way before the
> aux buffer.
>
> The restriction is referenced in a few places, but the most concise one [IMO]
> from the spec is for Gen9. Gen8 8 loosens the restriction in that it only
> requires this for non-msrt surface.
>
> When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must
> be used.
>
> With the code before the miptree layout flag rework (patches preceding this),
> accomplishing this workaround is very difficult.
>
> Cc: Anuj Phogat <anuj.phogat at gmail.com>
> Cc: Neil Roberts <neil at linux.intel.com>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 16 ++++++++++------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 ++++++++++++---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 +++-
> 3 files changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 72b02a2..b51c7c7 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -41,8 +41,13 @@
>
> static unsigned int
> intel_horizontal_texture_alignment_unit(struct brw_context *brw,
> - struct intel_mipmap_tree *mt)
> + struct intel_mipmap_tree *mt,
> + uint32_t layout_flags)
> {
> +
Extra newline.
> + if (layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16)
> + return 16;
> +
> /**
> * From the "Alignment Unit Size" section of various specs, namely:
> * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
> @@ -91,9 +96,6 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
> if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
> return 8;
>
> - if (brw->gen == 8 && mt->mcs_mt && mt->num_samples <= 1)
> - return 16;
> -
> return 4;
> }
>
> @@ -459,7 +461,8 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
> }
>
> void
> -brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
> +brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt,
> + uint32_t layout_flags)
> {
> bool multisampled = mt->num_samples > 1;
> bool gen6_hiz_or_stencil = false;
> @@ -492,8 +495,9 @@ brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
> mt->align_w = 128 / mt->cpp;
> mt->align_h = 32;
> }
> + assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
> } else {
> - mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
> + mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
> mt->align_h =
> intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
> }
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 75ee19a..a1ac0cf 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -475,7 +475,10 @@ intel_miptree_create_layout(struct brw_context *brw,
> if (layout_flags & MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD)
> mt->array_layout = ALL_SLICES_AT_EACH_LOD;
>
> - brw_miptree_layout(brw, mt);
> + if (intel_miptree_is_fast_clear_capable(brw, mt))
> + layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
> +
> + brw_miptree_layout(brw, mt, layout_flags);
>
> if (mt->disable_aux_buffers)
> assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
> @@ -722,6 +725,7 @@ intel_miptree_create(struct brw_context *brw,
>
>
> if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
> + assert(mt->num_samples > 1);
> if (!intel_miptree_alloc_mcs(brw, mt, num_samples)) {
> intel_miptree_release(&mt);
> return NULL;
> @@ -734,8 +738,10 @@ intel_miptree_create(struct brw_context *brw,
> * clear actually occurs.
> */
> if (intel_is_non_msrt_mcs_tile_supported(brw, mt->tiling) &&
> - intel_miptree_is_fast_clear_capable(brw, mt))
> + intel_miptree_is_fast_clear_capable(brw, mt)) {
> mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
> + assert(brw->gen < 8 || mt->align_w == 16);
> + }
>
> return mt;
> }
> @@ -1446,6 +1452,9 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> unsigned mcs_height =
> ALIGN(mt->logical_height0, height_divisor) / height_divisor;
> assert(mt->logical_depth0 == 1);
> + uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
> + if (brw->gen >= 8)
> + layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
> mt->mcs_mt = intel_miptree_create(brw,
> mt->target,
> format,
> @@ -1456,7 +1465,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> mt->logical_depth0,
> 0 /* num_samples */,
> INTEL_MIPTREE_TILING_Y,
> - MIPTREE_LAYOUT_ACCELERATED_UPLOAD);
> + layout_flags);
>
> return mt->mcs_mt;
> }
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index ccb6d72..bc1802e 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -532,6 +532,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
> #define MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD (1<<1)
> #define MIPTREE_LAYOUT_FOR_BO (1<<2)
> #define MIPTREE_LAYOUT_DISABLE_AUX (1<<3)
> +#define MIPTREE_LAYOUT_FORCE_HALIGN16 (1<<4)
I was about to comment this earlier in the series - usually we have
spaces around <<. Jordan and Anuj already reviewed the series and I just
wanted to skim through out of curiosity. Just something I happened to notice
in case you didn't push yet.
> struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
> GLenum target,
> mesa_format format,
> @@ -757,7 +758,8 @@ brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
> const struct intel_mipmap_tree *mt,
> unsigned level);
>
> -void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
> +void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt,
> + uint32_t layout_flags);
>
> void *intel_miptree_map_raw(struct brw_context *brw,
> struct intel_mipmap_tree *mt);
> --
> 2.4.2
>
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