[Mesa-dev] [PATCH 1/3] i965: Drop "Vector Mask Enable" bit from 3DSTATE_GS on Gen8+.
ben at bwidawsk.net
Fri May 29 15:04:30 PDT 2015
On Fri, May 29, 2015 at 12:26:38PM -0700, Kenneth Graunke wrote:
> The documentation makes it pretty clear that we shouldn't use this:
> "Under normal conditions SW shall specify DMask, as the GS stage
> will provide a Dispatch Mask appropriate to SIMD4x2 or SIMD8 thread
> execution (as a function of dispatch mode). E.g., for SIMD4x2
> execution, the GS stage will generate a Dispatch Mask that is equal
> to what the EU would use as the Vector Mask. For SIMD8 execution
> there is no known usage model for use of Vector Mask (as there is
> for PS shaders)."
> I also managed to find descriptions of DMask and VMask, in the "State
> Register" (sr0.2/3) field descriptions:
> "Dispatch Mask (DMask). This 32-bit field specifies which channels
> are active at Dispatch time."
> "Vector Mask (VMask). This 32-bit field contains, for each 4-bit
> group, the OR of the corresponding 4-bit group in the dispatch
> SIMD4x2 shaders process one or two vec4 values, with each 4-bit group
> corresponding to xyzw channel enables (either all on, or all off).
> Thus, DMask = VMask in SIMD4x2 mode. But in SIMD8 mode, 4-bit groups
> are meaningless, so it just messes up your values.
Just making sure you're reading this the same way I am, DMask == VMask for
SIMD4x2. VMask shouldn't be used for SIMD8.
While here, you've probably seen this before, but I just noticed for SIMD8 GS on
"Not valid for objects with more than 6 vertices per object."
Probably we don't care, but SPF might be effected by this patch, broken, or
fixed by this - I can't quite tell which.
This seems fine to me though.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> src/mesa/drivers/dri/i965/gen8_gs_state.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
> I'm working on SIMD8 geometry shader support. These are a few simple patches
> that are pretty straightforward and could be landed on their own.
> diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
> index 6a0e215..0763e91 100644
> --- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
> @@ -48,8 +48,7 @@ gen8_upload_gs_state(struct brw_context *brw)
> OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
> - OUT_BATCH(GEN6_GS_VECTOR_MASK_ENABLE |
> - brw->geometry_program->VerticesIn |
> + OUT_BATCH(brw->geometry_program->VerticesIn |
> ((ALIGN(stage_state->sampler_count, 4)/4) <<
> GEN6_GS_SAMPLER_COUNT_SHIFT) |
> ((prog_data->base.binding_table.size_bytes / 4) <<
Ben Widawsky, Intel Open Source Technology Center
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