[Mesa-dev] [PATCH 17/24] i965: Replace HW_REG with ARF/GRF.
Matt Turner
mattst88 at gmail.com
Mon Nov 2 16:29:27 PST 2015
HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to
look at different fields for type, abs, negate, writemask, swizzle, and
a second file. They also caused annoying problems like immediate sources
being considered scheduling barriers (commit 6148e94e2) and other such
nonsense.
Instead use ARF/GRF/MRF for fixed registers in those files.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 118 ++++++++----------
src/mesa/drivers/dri/i965/brw_fs.h | 5 +-
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 3 +-
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 3 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 7 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 5 +-
src/mesa/drivers/dri/i965/brw_ir_fs.h | 9 +-
src/mesa/drivers/dri/i965/brw_ir_vec4.h | 6 +-
.../drivers/dri/i965/brw_schedule_instructions.cpp | 53 +++-----
src/mesa/drivers/dri/i965/brw_shader.cpp | 8 +-
src/mesa/drivers/dri/i965/brw_shader.h | 5 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 137 +++++++++------------
src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 3 +-
13 files changed, 154 insertions(+), 208 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 92a9437..6eeafd5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -76,7 +76,8 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
/* This will be the case for almost all instructions. */
switch (dst.file) {
case VGRF:
- case HW_REG:
+ case ARF:
+ case GRF:
case MRF:
case ATTR:
this->regs_written = DIV_ROUND_UP(dst.component_size(exec_size),
@@ -422,7 +423,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
fs_reg::fs_reg(struct brw_reg reg) :
backend_reg(reg)
{
- this->file = HW_REG;
+ this->file = (enum register_file)reg.file;
this->reg_offset = 0;
this->subreg_offset = 0;
this->reladdr = NULL;
@@ -438,24 +439,17 @@ fs_reg::fs_reg(struct brw_reg reg) :
bool
fs_reg::equals(const fs_reg &r) const
{
- return (file == r.file &&
- nr == r.nr &&
+ return (memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
reg_offset == r.reg_offset &&
subreg_offset == r.subreg_offset &&
- type == r.type &&
- negate == r.negate &&
- abs == r.abs &&
!reladdr && !r.reladdr &&
- (file != HW_REG ||
- memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0) &&
- (file != IMM || d == r.d) &&
stride == r.stride);
}
fs_reg &
fs_reg::set_smear(unsigned subreg)
{
- assert(file != HW_REG && file != IMM);
+ assert(file != ARF && file != GRF && file != IMM);
subreg_offset = subreg * type_sz(type);
stride = 0;
return *this;
@@ -470,7 +464,7 @@ fs_reg::is_contiguous() const
unsigned
fs_reg::component_size(unsigned width) const
{
- const unsigned stride = (file != HW_REG ? this->stride :
+ const unsigned stride = ((file != ARF && file != GRF) ? this->stride :
hstride == 0 ? 0 :
1 << (hstride - 1));
return MAX2(width * stride, 1) * type_sz(type);
@@ -839,9 +833,10 @@ fs_inst::regs_read(int arg) const
case UNIFORM:
case IMM:
return 1;
+ case ARF:
+ case GRF:
case VGRF:
case ATTR:
- case HW_REG:
return DIV_ROUND_UP(components_read(arg) *
src[arg].component_size(exec_size),
REG_SIZE);
@@ -1520,12 +1515,12 @@ fs_visitor::assign_urb_setup()
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->opcode == FS_OPCODE_LINTERP) {
- assert(inst->src[1].file == HW_REG);
+ assert(inst->src[1].file == GRF);
inst->src[1].nr += urb_start;
}
if (inst->opcode == FS_OPCODE_CINTERP) {
- assert(inst->src[0].file == HW_REG);
+ assert(inst->src[0].file == GRF);
inst->src[0].nr += urb_start;
}
}
@@ -2680,7 +2675,7 @@ fs_visitor::emit_repclear_shader()
assign_curb_setup();
/* Now that we have the uniform assigned, go ahead and force it to a vec4. */
- assert(mov->src[0].file == HW_REG);
+ assert(mov->src[0].file == GRF);
mov->src[0] = brw_vec4_grf(mov->src[0].nr, 0);
}
@@ -2759,10 +2754,7 @@ clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len)
/* Clear the flag for registers that actually got read (as expected). */
for (int i = 0; i < inst->sources; i++) {
int grf;
- if (inst->src[i].file == VGRF) {
- grf = inst->src[i].nr;
- } else if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ if (inst->src[i].file == VGRF || inst->src[i].file == GRF) {
grf = inst->src[i].nr;
} else {
continue;
@@ -4469,6 +4461,9 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
fprintf(file, "+%d.%d",
inst->dst.reg_offset, inst->dst.subreg_offset);
break;
+ case GRF:
+ fprintf(file, "g%d", inst->dst.nr);
+ break;
case MRF:
fprintf(file, "m%d", inst->dst.nr);
break;
@@ -4481,29 +4476,23 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case ATTR:
fprintf(file, "***attr%d***", inst->dst.nr + inst->dst.reg_offset);
break;
- case HW_REG:
- if (inst->dst.brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
- switch (inst->dst.nr) {
- case BRW_ARF_NULL:
- fprintf(file, "null");
- break;
- case BRW_ARF_ADDRESS:
- fprintf(file, "a0.%d", inst->dst.subnr);
- break;
- case BRW_ARF_ACCUMULATOR:
- fprintf(file, "acc%d", inst->dst.subnr);
- break;
- case BRW_ARF_FLAG:
- fprintf(file, "f%d.%d", inst->dst.nr & 0xf,
- inst->dst.subnr);
- break;
- default:
- fprintf(file, "arf%d.%d", inst->dst.nr & 0xf,
- inst->dst.subnr);
- break;
- }
- } else {
- fprintf(file, "hw_reg%d", inst->dst.nr);
+ case ARF:
+ switch (inst->dst.nr) {
+ case BRW_ARF_NULL:
+ fprintf(file, "null");
+ break;
+ case BRW_ARF_ADDRESS:
+ fprintf(file, "a0.%d", inst->dst.subnr);
+ break;
+ case BRW_ARF_ACCUMULATOR:
+ fprintf(file, "acc%d", inst->dst.subnr);
+ break;
+ case BRW_ARF_FLAG:
+ fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
+ break;
+ default:
+ fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
+ break;
}
if (inst->dst.subnr)
fprintf(file, "+%d", inst->dst.subnr);
@@ -4526,6 +4515,9 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
fprintf(file, "+%d.%d", inst->src[i].reg_offset,
inst->src[i].subreg_offset);
break;
+ case GRF:
+ fprintf(file, "g%d", inst->src[i].nr);
+ break;
case MRF:
fprintf(file, "***m%d***", inst->src[i].nr);
break;
@@ -4569,29 +4561,23 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
break;
}
break;
- case HW_REG:
- if (inst->src[i].brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
- switch (inst->src[i].nr) {
- case BRW_ARF_NULL:
- fprintf(file, "null");
- break;
- case BRW_ARF_ADDRESS:
- fprintf(file, "a0.%d", inst->src[i].subnr);
- break;
- case BRW_ARF_ACCUMULATOR:
- fprintf(file, "acc%d", inst->src[i].subnr);
- break;
- case BRW_ARF_FLAG:
- fprintf(file, "f%d.%d", inst->src[i].nr & 0xf,
- inst->src[i].subnr);
- break;
- default:
- fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf,
- inst->src[i].subnr);
- break;
- }
- } else {
- fprintf(file, "hw_reg%d", inst->src[i].nr);
+ case ARF:
+ switch (inst->src[i].nr) {
+ case BRW_ARF_NULL:
+ fprintf(file, "null");
+ break;
+ case BRW_ARF_ADDRESS:
+ fprintf(file, "a0.%d", inst->src[i].subnr);
+ break;
+ case BRW_ARF_ACCUMULATOR:
+ fprintf(file, "acc%d", inst->src[i].subnr);
+ break;
+ case BRW_ARF_FLAG:
+ fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
+ break;
+ default:
+ fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
+ break;
}
if (inst->src[i].subnr)
fprintf(file, "+%d", inst->src[i].subnr);
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 1693349..3ada969 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -70,9 +70,10 @@ offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
switch (reg.file) {
case BAD_FILE:
break;
- case VGRF:
+ case ARF:
+ case GRF:
case MRF:
- case HW_REG:
+ case VGRF:
case ATTR:
return byte_offset(reg,
delta * reg.component_size(bld.dispatch_width()));
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index cb01833..880d08b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -387,7 +387,8 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
switch (entry->src.file) {
case UNIFORM:
case BAD_FILE:
- case HW_REG:
+ case ARF:
+ case GRF:
inst->src[arg].reg_offset = entry->src.reg_offset;
inst->src[arg].subreg_offset = entry->src.subreg_offset;
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index ee31cb6..cae38fc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -226,7 +226,8 @@ fs_visitor::opt_cse_local(bblock_t *block)
foreach_inst_in_block(fs_inst, inst, block) {
/* Skip some cases. */
if (is_expression(this, inst) && !inst->is_partial_write() &&
- (inst->dst.file != HW_REG || inst->dst.is_null()))
+ ((inst->dst.file != ARF && inst->dst.file != GRF) ||
+ inst->dst.is_null()))
{
bool found = false;
bool negate = false;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 654bb1c..a59439f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -37,6 +37,9 @@ static enum brw_reg_file
brw_file_from_reg(fs_reg *reg)
{
switch (reg->file) {
+ case ARF:
+ return BRW_ARCHITECTURE_REGISTER_FILE;
+ case GRF:
case VGRF:
return BRW_GENERAL_REGISTER_FILE;
case MRF:
@@ -44,7 +47,6 @@ brw_file_from_reg(fs_reg *reg)
case IMM:
return BRW_IMMEDIATE_VALUE;
case BAD_FILE:
- case HW_REG:
case ATTR:
case UNIFORM:
unreachable("not reached");
@@ -118,7 +120,8 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
unreachable("not reached");
}
break;
- case HW_REG:
+ case ARF:
+ case GRF:
brw_reg = *static_cast<struct brw_reg *>(reg);
break;
case BAD_FILE:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index e2234d1..f548117 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -366,13 +366,12 @@ void fs_visitor::calculate_payload_ranges(int payload_node_count,
else
use_ip = ip;
- /* Note that UNIFORM args have been turned into FIXED_HW_REG by
+ /* Note that UNIFORM args have been turned into GRF by
* assign_curbe_setup(), and interpolation uses fixed hardware regs from
* the start (see interp_reg()).
*/
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ if (inst->src[i].file == GRF) {
int node_nr = inst->src[i].nr;
if (node_nr >= payload_node_count)
continue;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index a3b3a4f..3d038f8 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -97,8 +97,9 @@ byte_offset(fs_reg reg, unsigned delta)
case MRF:
reg.nr += delta / 32;
break;
+ case ARF:
+ case GRF:
case IMM:
- case HW_REG:
case UNIFORM:
assert(delta == 0);
}
@@ -121,7 +122,8 @@ horiz_offset(fs_reg reg, unsigned delta)
case MRF:
case ATTR:
return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
- case HW_REG:
+ case ARF:
+ case GRF:
assert(delta == 0);
}
return reg;
@@ -163,8 +165,9 @@ half(fs_reg reg, unsigned idx)
case MRF:
return horiz_offset(reg, 8 * idx);
+ case ARF:
+ case GRF:
case ATTR:
- case HW_REG:
unreachable("Cannot take half of this register type");
}
return reg;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index d3f0d61..f6c7595 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -68,7 +68,8 @@ retype(src_reg reg, enum brw_reg_type type)
static inline src_reg
offset(src_reg reg, unsigned delta)
{
- assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
+ assert(delta == 0 ||
+ (reg.file != ARF && reg.file != GRF && reg.file != IMM));
reg.reg_offset += delta;
return reg;
}
@@ -132,7 +133,8 @@ retype(dst_reg reg, enum brw_reg_type type)
static inline dst_reg
offset(dst_reg reg, unsigned delta)
{
- assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
+ assert(delta == 0 ||
+ (reg.file != ARF && reg.file != GRF && reg.file != IMM));
reg.reg_offset += delta;
return reg;
}
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 345c9c6..98a5f5c 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -585,8 +585,7 @@ fs_instruction_scheduler::count_reads_remaining(backend_instruction *be)
if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]++;
- } else if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->src[i].file == GRF) {
if (inst->src[i].nr >= hw_reg_count)
continue;
@@ -670,8 +669,7 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be)
if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]--;
- } else if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE &&
+ } else if (inst->src[i].file == GRF &&
inst->src[i].nr < hw_reg_count) {
for (int off = 0; off < inst->regs_read(i); off++)
hw_reads_remaining[inst->src[i].nr + off]--;
@@ -700,8 +698,7 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be)
reads_remaining[inst->src[i].nr] == 1)
benefit += v->alloc.sizes[inst->src[i].nr];
- if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE &&
+ if (inst->src[i].file == GRF &&
inst->src[i].nr < hw_reg_count) {
for (int off = 0; off < inst->regs_read(i); off++) {
int reg = inst->src[i].nr + off;
@@ -960,9 +957,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], n);
}
}
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == GRF) {
if (post_reg_alloc) {
int size = reg_width;
if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0)
@@ -976,9 +971,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_accumulator_write, n);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF);
add_barrier_deps(n);
}
@@ -1028,8 +1021,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_mrf_write[reg], n);
last_mrf_write[reg] = n;
}
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == GRF) {
if (post_reg_alloc) {
for (int r = 0; r < reg_width; r++)
last_grf_write[inst->dst.nr + r] = n;
@@ -1089,9 +1081,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(n, last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], 0);
}
}
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == GRF) {
if (post_reg_alloc) {
int size = reg_width;
if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0)
@@ -1105,9 +1095,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(n, last_accumulator_write, 0);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF);
add_barrier_deps(n);
}
@@ -1156,8 +1144,7 @@ fs_instruction_scheduler::calculate_deps()
last_mrf_write[reg] = n;
}
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == GRF) {
if (post_reg_alloc) {
for (int r = 0; r < reg_width; r++)
last_grf_write[inst->dst.nr + r] = n;
@@ -1225,18 +1212,14 @@ vec4_instruction_scheduler::calculate_deps()
if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(last_grf_write[inst->src[i].nr + j], n);
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == GRF) {
add_dep(last_fixed_grf_write, n);
} else if (inst->src[i].is_accumulator()) {
assert(last_accumulator_write);
add_dep(last_accumulator_write, n);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
/* No reads from MRF, and ATTR is already translated away */
assert(inst->src[i].file != MRF &&
inst->src[i].file != ATTR);
@@ -1273,8 +1256,7 @@ vec4_instruction_scheduler::calculate_deps()
} else if (inst->dst.file == MRF) {
add_dep(last_mrf_write[inst->dst.nr], n);
last_mrf_write[inst->dst.nr] = n;
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == GRF) {
last_fixed_grf_write = n;
} else if (inst->dst.is_accumulator()) {
add_dep(last_accumulator_write, n);
@@ -1323,17 +1305,13 @@ vec4_instruction_scheduler::calculate_deps()
if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(n, last_grf_write[inst->src[i].nr + j]);
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == GRF) {
add_dep(n, last_fixed_grf_write);
} else if (inst->src[i].is_accumulator()) {
add_dep(n, last_accumulator_write);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF &&
inst->src[i].file != ATTR);
add_barrier_deps(n);
@@ -1366,8 +1344,7 @@ vec4_instruction_scheduler::calculate_deps()
last_grf_write[inst->dst.nr + j] = n;
} else if (inst->dst.file == MRF) {
last_mrf_write[inst->dst.nr] = n;
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == GRF) {
last_fixed_grf_write = n;
} else if (inst->dst.is_accumulator()) {
last_accumulator_write = n;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 2566022..f2da164 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -727,18 +727,14 @@ backend_reg::is_negative_one() const
bool
backend_reg::is_null() const
{
- return file == HW_REG &&
- brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE &&
- nr == BRW_ARF_NULL;
+ return file == ARF && nr == BRW_ARF_NULL;
}
bool
backend_reg::is_accumulator() const
{
- return file == HW_REG &&
- brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE &&
- nr == BRW_ARF_ACCUMULATOR;
+ return file == ARF && nr == BRW_ARF_ACCUMULATOR;
}
bool
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index e6c63a9..a59c953 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -39,10 +39,11 @@
#define MAX_VGRF_SIZE 16
enum PACKED register_file {
- VGRF,
+ ARF,
+ GRF,
MRF,
IMM,
- HW_REG, /* a struct brw_reg */
+ VGRF,
ATTR,
UNIFORM, /* prog_data->params[reg] */
BAD_FILE,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 8672614..bb5c7ac 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -119,7 +119,7 @@ src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
src_reg::src_reg(struct brw_reg reg) :
backend_reg(reg)
{
- this->file = HW_REG;
+ this->file = reg.file;
this->reg_offset = 0;
this->reladdr = NULL;
}
@@ -180,7 +180,7 @@ dst_reg::dst_reg(register_file file, int nr, brw_reg_type type,
dst_reg::dst_reg(struct brw_reg reg) :
backend_reg(reg)
{
- this->file = HW_REG;
+ this->file = reg.file;
this->reg_offset = 0;
this->reladdr = NULL;
}
@@ -198,17 +198,10 @@ dst_reg::dst_reg(const src_reg ®) :
bool
dst_reg::equals(const dst_reg &r) const
{
- return (file == r.file &&
- nr == r.nr &&
+ return (memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
reg_offset == r.reg_offset &&
- type == r.type &&
- negate == r.negate &&
- abs == r.abs &&
- writemask == r.writemask &&
(reladdr == r.reladdr ||
- (reladdr && r.reladdr && reladdr->equals(*r.reladdr))) &&
- (file != HW_REG ||
- memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0));
+ (reladdr && r.reladdr && reladdr->equals(*r.reladdr))));
}
bool
@@ -342,17 +335,9 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
bool
src_reg::equals(const src_reg &r) const
{
- return (file == r.file &&
- nr == r.nr &&
+ return (memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
reg_offset == r.reg_offset &&
- type == r.type &&
- negate == r.negate &&
- abs == r.abs &&
- swizzle == r.swizzle &&
- !reladdr && !r.reladdr &&
- (file != HW_REG ||
- memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0) &&
- (file != IMM || d == r.d));
+ !reladdr && !r.reladdr);
}
bool
@@ -440,7 +425,9 @@ vec4_visitor::opt_reduce_swizzle()
bool progress = false;
foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == BAD_FILE || inst->dst.file == HW_REG ||
+ if (inst->dst.file == BAD_FILE ||
+ inst->dst.file == ARF ||
+ inst->dst.file == GRF ||
inst->is_send_from_grf())
continue;
@@ -915,7 +902,7 @@ vec4_visitor::opt_set_dependency_control()
int reg = inst->src[i].nr + inst->src[i].reg_offset;
if (inst->src[i].file == VGRF) {
last_grf_write[reg] = NULL;
- } else if (inst->src[i].file == HW_REG) {
+ } else if (inst->src[i].file == GRF) {
memset(last_grf_write, 0, sizeof(last_grf_write));
break;
}
@@ -932,7 +919,7 @@ vec4_visitor::opt_set_dependency_control()
* against a previous one writing to its destination.
*/
int reg = inst->dst.nr + inst->dst.reg_offset;
- if (inst->dst.file == VGRF) {
+ if (inst->dst.file == VGRF || inst->dst.file == GRF) {
if (last_grf_write[reg] &&
!(inst->dst.writemask & grf_channels_written[reg])) {
last_grf_write[reg]->no_dd_clear = true;
@@ -954,11 +941,6 @@ vec4_visitor::opt_set_dependency_control()
last_mrf_write[reg] = inst;
mrf_channels_written[reg] |= inst->dst.writemask;
- } else if (inst->dst.nr == HW_REG) {
- if (inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE)
- memset(last_grf_write, 0, sizeof(last_grf_write));
- if (inst->dst.brw_reg::file == BRW_MESSAGE_REGISTER_FILE)
- memset(last_mrf_write, 0, sizeof(last_mrf_write));
}
}
}
@@ -986,11 +968,8 @@ vec4_instruction::can_reswizzle(const struct brw_device_info *devinfo,
if (mlen > 0)
return false;
- /* We can't use swizzles on the accumulator and that's really the only
- * HW_REG we would care to reswizzle so just disallow them all.
- */
for (int i = 0; i < 3; i++) {
- if (src[i].file == HW_REG)
+ if (src[i].is_accumulator())
return false;
}
@@ -1382,32 +1361,29 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case VGRF:
fprintf(file, "vgrf%d.%d", inst->dst.nr, inst->dst.reg_offset);
break;
+ case GRF:
+ fprintf(file, "g%d", inst->dst.nr);
+ break;
case MRF:
fprintf(file, "m%d", inst->dst.nr);
break;
- case HW_REG:
- if (inst->dst.brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
- switch (inst->dst.nr) {
- case BRW_ARF_NULL:
- fprintf(file, "null");
- break;
- case BRW_ARF_ADDRESS:
- fprintf(file, "a0.%d", inst->dst.subnr);
- break;
- case BRW_ARF_ACCUMULATOR:
- fprintf(file, "acc%d", inst->dst.subnr);
- break;
- case BRW_ARF_FLAG:
- fprintf(file, "f%d.%d", inst->dst.nr & 0xf,
- inst->dst.subnr);
- break;
- default:
- fprintf(file, "arf%d.%d", inst->dst.nr & 0xf,
- inst->dst.subnr);
- break;
- }
- } else {
- fprintf(file, "hw_reg%d", inst->dst.nr);
+ case ARF:
+ switch (inst->dst.nr) {
+ case BRW_ARF_NULL:
+ fprintf(file, "null");
+ break;
+ case BRW_ARF_ADDRESS:
+ fprintf(file, "a0.%d", inst->dst.subnr);
+ break;
+ case BRW_ARF_ACCUMULATOR:
+ fprintf(file, "acc%d", inst->dst.subnr);
+ break;
+ case BRW_ARF_FLAG:
+ fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
+ break;
+ default:
+ fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
+ break;
}
if (inst->dst.subnr)
fprintf(file, "+%d", inst->dst.subnr);
@@ -1445,6 +1421,9 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case VGRF:
fprintf(file, "vgrf%d", inst->src[i].nr);
break;
+ case GRF:
+ fprintf(file, "g%d", inst->src[i].nr);
+ break;
case ATTR:
fprintf(file, "attr%d", inst->src[i].nr);
break;
@@ -1474,29 +1453,23 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
break;
}
break;
- case HW_REG:
- if (inst->src[i].brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) {
- switch (inst->src[i].nr) {
- case BRW_ARF_NULL:
- fprintf(file, "null");
- break;
- case BRW_ARF_ADDRESS:
- fprintf(file, "a0.%d", inst->src[i].subnr);
- break;
- case BRW_ARF_ACCUMULATOR:
- fprintf(file, "acc%d", inst->src[i].subnr);
- break;
- case BRW_ARF_FLAG:
- fprintf(file, "f%d.%d", inst->src[i].nr & 0xf,
- inst->src[i].subnr);
- break;
- default:
- fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf,
- inst->src[i].subnr);
- break;
- }
- } else {
- fprintf(file, "hw_reg%d", inst->src[i].nr);
+ case ARF:
+ switch (inst->src[i].nr) {
+ case BRW_ARF_NULL:
+ fprintf(file, "null");
+ break;
+ case BRW_ARF_ADDRESS:
+ fprintf(file, "a0.%d", inst->src[i].subnr);
+ break;
+ case BRW_ARF_ACCUMULATOR:
+ fprintf(file, "acc%d", inst->src[i].subnr);
+ break;
+ case BRW_ARF_FLAG:
+ fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
+ break;
+ default:
+ fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
+ break;
}
if (inst->src[i].subnr)
fprintf(file, "+%d", inst->src[i].subnr);
@@ -1810,7 +1783,8 @@ vec4_visitor::convert_to_hw_regs()
assert(!src.reladdr);
break;
- case HW_REG:
+ case ARF:
+ case GRF:
continue;
case BAD_FILE:
@@ -1842,7 +1816,8 @@ vec4_visitor::convert_to_hw_regs()
reg.writemask = dst.writemask;
break;
- case HW_REG:
+ case ARF:
+ case GRF:
reg = dst;
break;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
index cdb76e4..87f4db1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
@@ -143,7 +143,8 @@ vec4_visitor::opt_cse_local(bblock_t *block)
foreach_inst_in_block (vec4_instruction, inst, block) {
/* Skip some cases. */
if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
- (inst->dst.file != HW_REG || inst->dst.is_null()))
+ ((inst->dst.file != ARF && inst->dst.file != GRF) ||
+ inst->dst.is_null()))
{
bool found = false;
--
2.4.9
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