[Mesa-dev] [PATCH 14/24] i965: Rename GRF to VGRF.
Matt Turner
mattst88 at gmail.com
Mon Nov 2 16:29:24 PST 2015
The 2-bit hardware register file field is ARF, GRF, MRF, IMM.
Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to
mean an assigned general purpose register.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 104 ++++++++++-----------
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_builder.h | 4 +-
.../drivers/dri/i965/brw_fs_cmod_propagation.cpp | 2 +-
.../drivers/dri/i965/brw_fs_combine_constants.cpp | 4 +-
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 26 +++---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 6 +-
.../dri/i965/brw_fs_dead_code_eliminate.cpp | 6 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 +-
.../drivers/dri/i965/brw_fs_live_variables.cpp | 6 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 ++---
.../drivers/dri/i965/brw_fs_register_coalesce.cpp | 8 +-
.../dri/i965/brw_fs_saturate_propagation.cpp | 6 +-
src/mesa/drivers/dri/i965/brw_fs_validate.cpp | 4 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16 ++--
src/mesa/drivers/dri/i965/brw_ir_fs.h | 6 +-
.../drivers/dri/i965/brw_schedule_instructions.cpp | 26 +++---
src/mesa/drivers/dri/i965/brw_shader.h | 4 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 32 +++----
src/mesa/drivers/dri/i965/brw_vec4_builder.h | 2 +-
.../drivers/dri/i965/brw_vec4_cmod_propagation.cpp | 2 +-
.../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 14 +--
src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 4 +-
.../dri/i965/brw_vec4_dead_code_eliminate.cpp | 8 +-
.../drivers/dri/i965/brw_vec4_live_variables.cpp | 8 +-
.../drivers/dri/i965/brw_vec4_live_variables.h | 4 +-
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +-
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 26 +++---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 ++--
30 files changed, 193 insertions(+), 193 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index fecac13..91eaf61 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -75,7 +75,7 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
/* This will be the case for almost all instructions. */
switch (dst.file) {
- case GRF:
+ case VGRF:
case HW_REG:
case MRF:
case ATTR:
@@ -203,7 +203,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD;
int regs_written = 4 * (bld.dispatch_width() / 8) * scale;
- fs_reg vec4_result = fs_reg(GRF, alloc.allocate(regs_written), dst.type);
+ fs_reg vec4_result = fs_reg(VGRF, alloc.allocate(regs_written), dst.type);
fs_inst *inst = bld.emit(op, vec4_result, surf_index, vec4_offset);
inst->regs_written = regs_written;
@@ -232,7 +232,7 @@ fs_visitor::DEP_RESOLVE_MOV(const fs_builder &bld, int grf)
const fs_builder ubld = bld.annotate("send dependency resolve")
.half(0);
- ubld.MOV(ubld.null_reg_f(), fs_reg(GRF, grf, BRW_REGISTER_TYPE_F));
+ ubld.MOV(ubld.null_reg_f(), fs_reg(VGRF, grf, BRW_REGISTER_TYPE_F));
}
bool
@@ -285,12 +285,12 @@ fs_inst::is_send_from_grf() const
case SHADER_OPCODE_URB_READ_SIMD8:
return true;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
- return src[1].file == GRF;
+ return src[1].file == VGRF;
case FS_OPCODE_FB_WRITE:
- return src[0].file == GRF;
+ return src[0].file == VGRF;
default:
if (is_tex())
- return src[0].file == GRF;
+ return src[0].file == VGRF;
return false;
}
@@ -303,7 +303,7 @@ fs_inst::is_copy_payload(const brw::simple_allocator &grf_alloc) const
return false;
fs_reg reg = this->src[0];
- if (reg.file != GRF || reg.reg_offset != 0 || reg.stride == 0)
+ if (reg.file != VGRF || reg.reg_offset != 0 || reg.stride == 0)
return false;
if (grf_alloc.sizes[reg.nr] != this->regs_written)
@@ -526,7 +526,7 @@ fs_visitor::get_timestamp(const fs_builder &bld)
0),
BRW_REGISTER_TYPE_UD));
- fs_reg dst = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_reg dst = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
/* We want to read the 3 fields we care about even if it's not enabled in
* the dispatch.
@@ -581,7 +581,7 @@ fs_visitor::emit_shader_time_end()
fs_reg start = shader_start_time;
start.negate = true;
- fs_reg diff = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_reg diff = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
diff.set_smear(0);
const fs_builder cbld = ibld.group(1, 0);
@@ -822,7 +822,7 @@ fs_inst::regs_read(int arg) const
return 1;
default:
- if (is_tex() && arg == 0 && src[0].file == GRF)
+ if (is_tex() && arg == 0 && src[0].file == VGRF)
return mlen;
break;
}
@@ -833,7 +833,7 @@ fs_inst::regs_read(int arg) const
case UNIFORM:
case IMM:
return 1;
- case GRF:
+ case VGRF:
case ATTR:
case HW_REG:
return DIV_ROUND_UP(components_read(arg) *
@@ -935,7 +935,7 @@ fs_reg
fs_visitor::vgrf(const glsl_type *const type)
{
int reg_width = dispatch_width / 8;
- return fs_reg(GRF, alloc.allocate(type_size_scalar(type) * reg_width),
+ return fs_reg(VGRF, alloc.allocate(type_size_scalar(type) * reg_width),
brw_type_for_base_type(type));
}
@@ -1280,9 +1280,9 @@ fs_visitor::emit_sampleid_setup()
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type));
if (key->compute_sample_id) {
- fs_reg t1(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_D);
+ fs_reg t1(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_D);
t1.set_smear(0);
- fs_reg t2(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_W);
+ fs_reg t2(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_W);
/* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
* 8x multisampling, subspan 0 will represent sample N (where N
@@ -1608,14 +1608,14 @@ fs_visitor::split_virtual_grfs()
/* Mark all used registers as fully splittable */
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
int reg = vgrf_to_reg[inst->dst.nr];
for (unsigned j = 1; j < this->alloc.sizes[inst->dst.nr]; j++)
split_points[reg + j] = true;
}
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
int reg = vgrf_to_reg[inst->src[i].nr];
for (unsigned j = 1; j < this->alloc.sizes[inst->src[i].nr]; j++)
split_points[reg + j] = true;
@@ -1624,13 +1624,13 @@ fs_visitor::split_virtual_grfs()
}
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
int reg = vgrf_to_reg[inst->dst.nr] + inst->dst.reg_offset;
for (int j = 1; j < inst->regs_written; j++)
split_points[reg + j] = false;
}
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
int reg = vgrf_to_reg[inst->src[i].nr] + inst->src[i].reg_offset;
for (int j = 1; j < inst->regs_read(i); j++)
split_points[reg + j] = false;
@@ -1677,14 +1677,14 @@ fs_visitor::split_virtual_grfs()
assert(reg == reg_count);
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
reg = vgrf_to_reg[inst->dst.nr] + inst->dst.reg_offset;
inst->dst.nr = new_virtual_grf[reg];
inst->dst.reg_offset = new_reg_offset[reg];
assert((unsigned)new_reg_offset[reg] < alloc.sizes[new_virtual_grf[reg]]);
}
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
reg = vgrf_to_reg[inst->src[i].nr] + inst->src[i].reg_offset;
inst->src[i].nr = new_virtual_grf[reg];
inst->src[i].reg_offset = new_reg_offset[reg];
@@ -1713,11 +1713,11 @@ fs_visitor::compact_virtual_grfs()
/* Mark which virtual GRFs are used. */
foreach_block_and_inst(block, const fs_inst, inst, cfg) {
- if (inst->dst.file == GRF)
+ if (inst->dst.file == VGRF)
remap_table[inst->dst.nr] = 0;
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF)
+ if (inst->src[i].file == VGRF)
remap_table[inst->src[i].nr] = 0;
}
}
@@ -1742,11 +1742,11 @@ fs_visitor::compact_virtual_grfs()
/* Patch all the instructions to use the newly renumbered registers */
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->dst.file == GRF)
+ if (inst->dst.file == VGRF)
inst->dst.nr = remap_table[inst->dst.nr];
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF)
+ if (inst->src[i].file == VGRF)
inst->src[i].nr = remap_table[inst->src[i].nr];
}
}
@@ -1756,7 +1756,7 @@ fs_visitor::compact_virtual_grfs()
* think some random VGRF is delta_xy.
*/
for (unsigned i = 0; i < ARRAY_SIZE(delta_xy); i++) {
- if (delta_xy[i].file == GRF) {
+ if (delta_xy[i].file == VGRF) {
if (remap_table[delta_xy[i].nr] != -1) {
delta_xy[i].nr = remap_table[delta_xy[i].nr];
} else {
@@ -1931,7 +1931,7 @@ fs_visitor::demote_pull_constants()
}
/* Rewrite the instruction to use the temporary VGRF. */
- inst->src[i].file = GRF;
+ inst->src[i].file = VGRF;
inst->src[i].nr = dst.nr;
inst->src[i].reg_offset = 0;
}
@@ -2342,7 +2342,7 @@ fs_visitor::opt_register_renaming()
/* Rewrite instruction sources. */
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF &&
+ if (inst->src[i].file == VGRF &&
remap[inst->src[i].nr] != -1 &&
remap[inst->src[i].nr] != inst->src[i].nr) {
inst->src[i].nr = remap[inst->src[i].nr];
@@ -2353,7 +2353,7 @@ fs_visitor::opt_register_renaming()
const int dst = inst->dst.nr;
if (depth == 0 &&
- inst->dst.file == GRF &&
+ inst->dst.file == VGRF &&
alloc.sizes[inst->dst.nr] == inst->exec_size / 8 &&
!inst->is_partial_write()) {
if (remap[dst] == -1) {
@@ -2363,7 +2363,7 @@ fs_visitor::opt_register_renaming()
inst->dst.nr = remap[dst];
progress = true;
}
- } else if (inst->dst.file == GRF &&
+ } else if (inst->dst.file == VGRF &&
remap[dst] != -1 &&
remap[dst] != dst) {
inst->dst.nr = remap[dst];
@@ -2375,7 +2375,7 @@ fs_visitor::opt_register_renaming()
invalidate_live_intervals();
for (unsigned i = 0; i < ARRAY_SIZE(delta_xy); i++) {
- if (delta_xy[i].file == GRF && remap[delta_xy[i].nr] != -1) {
+ if (delta_xy[i].file == VGRF && remap[delta_xy[i].nr] != -1) {
delta_xy[i].nr = remap[delta_xy[i].nr];
}
}
@@ -2443,7 +2443,7 @@ fs_visitor::compute_to_mrf()
if (inst->opcode != BRW_OPCODE_MOV ||
inst->is_partial_write() ||
- inst->dst.file != MRF || inst->src[0].file != GRF ||
+ inst->dst.file != MRF || inst->src[0].file != VGRF ||
inst->dst.type != inst->src[0].type ||
inst->src[0].abs || inst->src[0].negate ||
!inst->src[0].is_contiguous() ||
@@ -2473,7 +2473,7 @@ fs_visitor::compute_to_mrf()
* rewrite the thing that made this GRF to write into the MRF.
*/
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
- if (scan_inst->dst.file == GRF &&
+ if (scan_inst->dst.file == VGRF &&
scan_inst->dst.nr == inst->src[0].nr) {
/* Found the last thing to write our reg we want to turn
* into a compute-to-MRF.
@@ -2529,7 +2529,7 @@ fs_visitor::compute_to_mrf()
*/
bool interfered = false;
for (int i = 0; i < scan_inst->sources; i++) {
- if (scan_inst->src[i].file == GRF &&
+ if (scan_inst->src[i].file == VGRF &&
scan_inst->src[i].nr == inst->src[0].nr &&
scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
interfered = true;
@@ -2724,7 +2724,7 @@ fs_visitor::remove_duplicate_mrf_writes()
}
/* Clear out any MRF move records whose sources got overwritten. */
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
for (unsigned int i = 0; i < ARRAY_SIZE(last_mrf_move); i++) {
if (last_mrf_move[i] &&
last_mrf_move[i]->src[0].nr == inst->dst.nr) {
@@ -2735,7 +2735,7 @@ fs_visitor::remove_duplicate_mrf_writes()
if (inst->opcode == BRW_OPCODE_MOV &&
inst->dst.file == MRF &&
- inst->src[0].file == GRF &&
+ inst->src[0].file == VGRF &&
!inst->is_partial_write()) {
last_mrf_move[inst->dst.nr] = inst;
}
@@ -2753,7 +2753,7 @@ clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len)
/* Clear the flag for registers that actually got read (as expected). */
for (int i = 0; i < inst->sources; i++) {
int grf;
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
grf = inst->src[i].nr;
} else if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
@@ -2823,7 +2823,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
* instruction but a MOV that might have left us an outstanding
* dependency has more latency than a MOV.
*/
- if (scan_inst->dst.file == GRF) {
+ if (scan_inst->dst.file == VGRF) {
for (int i = 0; i < scan_inst->regs_written; i++) {
int reg = scan_inst->dst.nr + i;
@@ -2889,7 +2889,7 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_ins
/* We insert our reads as late as possible since they're reading the
* result of a SEND, which has massive latency.
*/
- if (scan_inst->dst.file == GRF &&
+ if (scan_inst->dst.file == VGRF &&
scan_inst->dst.nr >= first_write_grf &&
scan_inst->dst.nr < first_write_grf + write_len &&
needs_dep[scan_inst->dst.nr - first_write_grf]) {
@@ -2922,7 +2922,7 @@ fs_visitor::insert_gen4_send_dependency_workarounds()
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->mlen != 0 && inst->dst.file == GRF) {
+ if (inst->mlen != 0 && inst->dst.file == VGRF) {
insert_gen4_pre_send_dependency_workarounds(block, inst);
insert_gen4_post_send_dependency_workarounds(block, inst);
progress = true;
@@ -2970,11 +2970,11 @@ fs_visitor::lower_uniform_pull_constant_loads()
/* We have to use a message header on Skylake to get SIMD4x2
* mode. Reserve space for the register.
*/
- offset = payload = fs_reg(GRF, alloc.allocate(2));
+ offset = payload = fs_reg(VGRF, alloc.allocate(2));
offset.reg_offset++;
inst->mlen = 2;
} else {
- offset = payload = fs_reg(GRF, alloc.allocate(1));
+ offset = payload = fs_reg(VGRF, alloc.allocate(1));
inst->mlen = 1;
}
@@ -3021,7 +3021,7 @@ fs_visitor::lower_load_payload()
if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD)
continue;
- assert(inst->dst.file == MRF || inst->dst.file == GRF);
+ assert(inst->dst.file == MRF || inst->dst.file == VGRF);
assert(inst->saturate == false);
fs_reg dst = inst->dst;
@@ -3141,7 +3141,7 @@ fs_visitor::lower_integer_multiplication()
* single MUL instruction with that value in the proper location.
*/
if (devinfo->gen < 7) {
- fs_reg imm(GRF, alloc.allocate(dispatch_width / 8),
+ fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8),
inst->dst.type);
ibld.MOV(imm, inst->src[1]);
ibld.MUL(inst->dst, imm, inst->src[0]);
@@ -3196,11 +3196,11 @@ fs_visitor::lower_integer_multiplication()
fs_reg orig_dst = inst->dst;
if (orig_dst.is_null() || orig_dst.file == MRF) {
- inst->dst = fs_reg(GRF, alloc.allocate(dispatch_width / 8),
+ inst->dst = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
inst->dst.type);
}
fs_reg low = inst->dst;
- fs_reg high(GRF, alloc.allocate(dispatch_width / 8),
+ fs_reg high(VGRF, alloc.allocate(dispatch_width / 8),
inst->dst.type);
if (devinfo->gen >= 7) {
@@ -3394,7 +3394,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
}
if (payload.aa_dest_stencil_reg) {
- sources[length] = fs_reg(GRF, bld.shader->alloc.allocate(1));
+ sources[length] = fs_reg(VGRF, bld.shader->alloc.allocate(1));
bld.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
.MOV(sources[length],
fs_reg(brw_vec8_grf(payload.aa_dest_stencil_reg, 0)));
@@ -3402,7 +3402,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
}
if (prog_data->uses_omask) {
- sources[length] = fs_reg(GRF, bld.shader->alloc.allocate(1),
+ sources[length] = fs_reg(VGRF, bld.shader->alloc.allocate(1),
BRW_REGISTER_TYPE_UD);
/* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
@@ -3468,7 +3468,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
fs_inst *load;
if (devinfo->gen >= 7) {
/* Send from the GRF */
- fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F);
+ fs_reg payload = fs_reg(VGRF, -1, BRW_REGISTER_TYPE_F);
load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size);
payload.nr = bld.shader->alloc.allocate(load->regs_written);
load->dst = payload;
@@ -3895,7 +3895,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
else
mlen = length * reg_width;
- const fs_reg src_payload = fs_reg(GRF, bld.shader->alloc.allocate(mlen),
+ const fs_reg src_payload = fs_reg(VGRF, bld.shader->alloc.allocate(mlen),
BRW_REGISTER_TYPE_F);
bld.LOAD_PAYLOAD(src_payload, sources, length, header_size);
@@ -4456,7 +4456,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
}
switch (inst->dst.file) {
- case GRF:
+ case VGRF:
fprintf(file, "vgrf%d", inst->dst.nr);
if (alloc.sizes[inst->dst.nr] != inst->regs_written ||
inst->dst.subreg_offset)
@@ -4513,7 +4513,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
if (inst->src[i].abs)
fprintf(file, "|");
switch (inst->src[i].file) {
- case GRF:
+ case VGRF:
fprintf(file, "vgrf%d", inst->src[i].nr);
if (alloc.sizes[inst->src[i].nr] != (unsigned)inst->regs_read(i) ||
inst->src[i].subreg_offset)
@@ -4902,7 +4902,7 @@ fs_visitor::fixup_3src_null_dest()
{
foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
if (inst->is_3src() && inst->dst.is_null()) {
- inst->dst = fs_reg(GRF, alloc.allocate(dispatch_width / 8),
+ inst->dst = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
inst->dst.type);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 8058b34..1693349 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -70,7 +70,7 @@ offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
switch (reg.file) {
case BAD_FILE:
break;
- case GRF:
+ case VGRF:
case MRF:
case HW_REG:
case ATTR:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index f121f34..5ca5eea 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -179,7 +179,7 @@ namespace brw {
assert(dispatch_width() <= 32);
if (n > 0)
- return dst_reg(GRF, shader->alloc.allocate(
+ return dst_reg(VGRF, shader->alloc.allocate(
DIV_ROUND_UP(n * type_sz(type) * dispatch_width(),
REG_SIZE)),
type);
@@ -595,7 +595,7 @@ namespace brw {
src_reg
fix_3src_operand(const src_reg &src) const
{
- if (src.file == GRF || src.file == UNIFORM || src.stride > 1) {
+ if (src.file == VGRF || src.file == UNIFORM || src.stride > 1) {
return src;
} else {
dst_reg expanded = vgrf(src.type);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp
index 883e8d2..8fdc959 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp
@@ -62,7 +62,7 @@ opt_cmod_propagation_local(bblock_t *block)
inst->opcode != BRW_OPCODE_MOV) ||
inst->predicate != BRW_PREDICATE_NONE ||
!inst->dst.is_null() ||
- inst->src[0].file != GRF ||
+ inst->src[0].file != VGRF ||
inst->src[0].abs)
continue;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
index 127cee4..0c115f5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
@@ -268,7 +268,7 @@ fs_visitor::opt_combine_constants()
/* Insert MOVs to load the constant values into GRFs. */
- fs_reg reg(GRF, alloc.allocate(dispatch_width / 8));
+ fs_reg reg(VGRF, alloc.allocate(dispatch_width / 8));
reg.stride = 0;
for (int i = 0; i < table.len; i++) {
struct imm *imm = &table.imm[i];
@@ -295,7 +295,7 @@ fs_visitor::opt_combine_constants()
for (int i = 0; i < table.len; i++) {
foreach_list_typed(reg_link, link, link, table.imm[i].uses) {
fs_reg *reg = link->reg;
- reg->file = GRF;
+ reg->file = VGRF;
reg->nr = table.imm[i].nr;
reg->subreg_offset = table.imm[i].subreg_offset;
reg->stride = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 7959413..cb01833 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -154,7 +154,7 @@ fs_copy_prop_dataflow::setup_initial_values()
/* Initialize the COPY and KILL sets. */
foreach_block (block, cfg) {
foreach_inst_in_block(fs_inst, inst, block) {
- if (inst->dst.file != GRF)
+ if (inst->dst.file != VGRF)
continue;
/* Mark ACP entries which are killed by this instruction. */
@@ -278,19 +278,19 @@ is_logic_op(enum opcode opcode)
bool
fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
{
- if (inst->src[arg].file != GRF)
+ if (inst->src[arg].file != VGRF)
return false;
if (entry->src.file == IMM)
return false;
- assert(entry->src.file == GRF || entry->src.file == UNIFORM ||
+ assert(entry->src.file == VGRF || entry->src.file == UNIFORM ||
entry->src.file == ATTR);
if (entry->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD)
return false;
- assert(entry->dst.file == GRF);
+ assert(entry->dst.file == VGRF);
if (inst->src[arg].nr != entry->dst.nr)
return false;
@@ -392,7 +392,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
inst->src[arg].subreg_offset = entry->src.subreg_offset;
break;
case ATTR:
- case GRF:
+ case VGRF:
{
/* In this case, we'll just leave the width alone. The source
* register could have different widths depending on how it is
@@ -456,10 +456,10 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
return false;
for (int i = inst->sources - 1; i >= 0; i--) {
- if (inst->src[i].file != GRF)
+ if (inst->src[i].file != VGRF)
continue;
- assert(entry->dst.file == GRF);
+ assert(entry->dst.file == VGRF);
if (inst->src[i].nr != entry->dst.nr)
continue;
@@ -652,8 +652,8 @@ static bool
can_propagate_from(fs_inst *inst)
{
return (inst->opcode == BRW_OPCODE_MOV &&
- inst->dst.file == GRF &&
- ((inst->src[0].file == GRF &&
+ inst->dst.file == VGRF &&
+ ((inst->src[0].file == VGRF &&
(inst->src[0].nr != inst->dst.nr ||
inst->src[0].reg_offset != inst->dst.reg_offset)) ||
inst->src[0].file == ATTR ||
@@ -675,7 +675,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block,
foreach_inst_in_block(fs_inst, inst, block) {
/* Try propagating into this instruction. */
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file != GRF)
+ if (inst->src[i].file != VGRF)
continue;
foreach_in_list(acp_entry, entry, &acp[inst->src[i].nr % ACP_HASH_SIZE]) {
@@ -688,7 +688,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block,
}
/* kill the destination from the ACP */
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
foreach_in_list_safe(acp_entry, entry, &acp[inst->dst.nr % ACP_HASH_SIZE]) {
if (inst->overwrites_reg(entry->dst)) {
entry->remove();
@@ -718,12 +718,12 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block,
entry->saturate = inst->saturate;
acp[entry->dst.nr % ACP_HASH_SIZE].push_tail(entry);
} else if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
- inst->dst.file == GRF) {
+ inst->dst.file == VGRF) {
int offset = 0;
for (int i = 0; i < inst->sources; i++) {
int effective_width = i < inst->header_size ? 8 : inst->exec_size;
int regs_written = effective_width / 8;
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
acp_entry *entry = ralloc(copy_prop_ctx, acp_entry);
entry->dst = inst->dst;
entry->dst.reg_offset = offset;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index 08f89d5..ee31cb6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -196,7 +196,7 @@ create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate)
header_size = 0;
}
- assert(src.file == GRF);
+ assert(src.file == VGRF);
payload = ralloc_array(bld.shader->mem_ctx, fs_reg, sources);
for (int i = 0; i < header_size; i++) {
payload[i] = src;
@@ -262,7 +262,7 @@ fs_visitor::opt_cse_local(bblock_t *block)
.at(block, entry->generator->next);
int written = entry->generator->regs_written;
- entry->tmp = fs_reg(GRF, alloc.allocate(written),
+ entry->tmp = fs_reg(VGRF, alloc.allocate(written),
entry->generator->dst.type);
create_copy_instr(ibld, entry->generator, entry->tmp, false);
@@ -320,7 +320,7 @@ fs_visitor::opt_cse_local(bblock_t *block)
/* Kill any AEB entries using registers that don't get reused any
* more -- a sure sign they'll fail operands_match().
*/
- if (src_reg->file == GRF && virtual_grf_end[src_reg->nr] < ip) {
+ if (src_reg->file == VGRF && virtual_grf_end[src_reg->nr] < ip) {
entry->remove();
ralloc_free(entry);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp
index 4b5548a..6b1d199 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp
@@ -52,7 +52,7 @@ fs_visitor::dead_code_eliminate()
sizeof(BITSET_WORD));
foreach_inst_in_block_reverse(fs_inst, inst, block) {
- if (inst->dst.file == GRF && !inst->has_side_effects()) {
+ if (inst->dst.file == VGRF && !inst->has_side_effects()) {
bool result_live = false;
if (inst->regs_written == 1) {
@@ -96,7 +96,7 @@ fs_visitor::dead_code_eliminate()
continue;
}
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
if (!inst->is_partial_write()) {
int var = live_intervals->var_from_reg(inst->dst);
for (int i = 0; i < inst->regs_written; i++) {
@@ -110,7 +110,7 @@ fs_visitor::dead_code_eliminate()
}
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
int var = live_intervals->var_from_reg(inst->src[i]);
for (int j = 0; j < inst->regs_read(i); j++) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index d7061be..ddeb528 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -37,7 +37,7 @@ static enum brw_reg_file
brw_file_from_reg(fs_reg *reg)
{
switch (reg->file) {
- case GRF:
+ case VGRF:
return BRW_GENERAL_REGISTER_FILE;
case MRF:
return BRW_MESSAGE_REGISTER_FILE;
@@ -61,7 +61,7 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
case MRF:
assert((reg->nr & ~(1 << 7)) < BRW_MAX_MRF(gen));
/* Fallthrough */
- case GRF:
+ case VGRF:
if (reg->stride == 0) {
brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
} else if (inst->exec_size < 8) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index ce066a9..80fb8c2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
@@ -117,7 +117,7 @@ fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst,
/* The def[] bitset marks when an initialization in a block completely
* screens off previous updates of that variable (VGRF channel).
*/
- if (inst->dst.file == GRF && !inst->is_partial_write()) {
+ if (inst->dst.file == VGRF && !inst->is_partial_write()) {
if (!BITSET_TEST(bd->use, var))
BITSET_SET(bd->def, var);
}
@@ -149,7 +149,7 @@ fs_live_variables::setup_def_use()
for (unsigned int i = 0; i < inst->sources; i++) {
fs_reg reg = inst->src[i];
- if (reg.file != GRF)
+ if (reg.file != VGRF)
continue;
for (int j = 0; j < inst->regs_read(i); j++) {
@@ -172,7 +172,7 @@ fs_live_variables::setup_def_use()
}
/* Set def[] for this instruction */
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
fs_reg reg = inst->dst;
for (int j = 0; j < inst->regs_written; j++) {
setup_one_write(bd, inst, ip, reg);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 611347c..1f04cb8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1116,7 +1116,7 @@ fs_visitor::emit_percomp(const fs_builder &bld, const fs_inst &inst,
fs_inst *new_inst = new(mem_ctx) fs_inst(inst);
new_inst->dst = offset(new_inst->dst, bld, i);
for (unsigned j = 0; j < new_inst->sources; j++)
- if (new_inst->src[j].file == GRF)
+ if (new_inst->src[j].file == VGRF)
new_inst->src[j] = offset(new_inst->src[j], bld, i);
bld.emit(new_inst);
@@ -1896,7 +1896,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg source = fs_reg(0);
int mlen = 1 * reg_width;
- fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
+ fs_reg src_payload = fs_reg(VGRF, alloc.allocate(mlen),
BRW_REGISTER_TYPE_UD);
bld.LOAD_PAYLOAD(src_payload, &source, 1, 0);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 99ccdb1..e2234d1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -35,7 +35,7 @@ using namespace brw;
static void
assign_reg(unsigned *reg_hw_locations, fs_reg *reg)
{
- if (reg->file == GRF) {
+ if (reg->file == VGRF) {
reg->nr = reg_hw_locations[reg->nr] + reg->reg_offset;
reg->reg_offset = 0;
}
@@ -584,7 +584,7 @@ fs_visitor::assign_regs(bool allow_spilling)
* that register and set it to the appropriate class.
*/
if (compiler->fs_reg_sets[rsi].aligned_pairs_class >= 0 &&
- this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF &&
+ this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == VGRF &&
this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].nr == i) {
c = compiler->fs_reg_sets[rsi].aligned_pairs_class;
}
@@ -644,11 +644,11 @@ fs_visitor::assign_regs(bool allow_spilling)
* destination interfere.
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->dst.file != GRF)
+ if (inst->dst.file != VGRF)
continue;
for (int i = 0; i < inst->sources; ++i) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr);
}
}
@@ -786,7 +786,7 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
for (unsigned int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
spill_costs[inst->src[i].nr] += loop_scale;
/* Register spilling logic assumes full-width registers; smeared
@@ -802,7 +802,7 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
}
}
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
spill_costs[inst->dst.nr] += inst->regs_written * loop_scale;
if (!inst->dst.is_contiguous()) {
@@ -821,13 +821,13 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
- if (inst->src[0].file == GRF)
+ if (inst->src[0].file == VGRF)
no_spill[inst->src[0].nr] = true;
break;
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GEN7_SCRATCH_READ:
- if (inst->dst.file == GRF)
+ if (inst->dst.file == VGRF)
no_spill[inst->dst.nr] = true;
break;
@@ -883,12 +883,12 @@ fs_visitor::spill_reg(int spill_reg)
*/
foreach_block_and_inst (block, fs_inst, inst, cfg) {
for (unsigned int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF &&
+ if (inst->src[i].file == VGRF &&
inst->src[i].nr == spill_reg) {
int regs_read = inst->regs_read(i);
int subset_spill_offset = (spill_offset +
REG_SIZE * inst->src[i].reg_offset);
- fs_reg unspill_dst(GRF, alloc.allocate(regs_read));
+ fs_reg unspill_dst(VGRF, alloc.allocate(regs_read));
inst->src[i].nr = unspill_dst.nr;
inst->src[i].reg_offset = 0;
@@ -898,11 +898,11 @@ fs_visitor::spill_reg(int spill_reg)
}
}
- if (inst->dst.file == GRF &&
+ if (inst->dst.file == VGRF &&
inst->dst.nr == spill_reg) {
int subset_spill_offset = (spill_offset +
REG_SIZE * inst->dst.reg_offset);
- fs_reg spill_src(GRF, alloc.allocate(inst->regs_written));
+ fs_reg spill_src(VGRF, alloc.allocate(inst->regs_written));
inst->dst.nr = spill_src.nr;
inst->dst.reg_offset = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp
index ce1d66e..4578ad5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp
@@ -70,11 +70,11 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
inst->is_partial_write() ||
inst->saturate ||
- inst->src[0].file != GRF ||
+ inst->src[0].file != VGRF ||
inst->src[0].negate ||
inst->src[0].abs ||
!inst->src[0].is_contiguous() ||
- inst->dst.file != GRF ||
+ inst->dst.file != VGRF ||
inst->dst.type != inst->src[0].type) {
return false;
}
@@ -250,7 +250,7 @@ fs_visitor::register_coalesce()
}
foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
- if (scan_inst->dst.file == GRF &&
+ if (scan_inst->dst.file == VGRF &&
scan_inst->dst.nr == src_reg) {
scan_inst->dst.nr = dst_reg;
scan_inst->dst.reg_offset =
@@ -258,7 +258,7 @@ fs_visitor::register_coalesce()
}
for (int j = 0; j < scan_inst->sources; j++) {
- if (scan_inst->src[j].file == GRF &&
+ if (scan_inst->src[j].file == VGRF &&
scan_inst->src[j].nr == src_reg) {
scan_inst->src[j].nr = dst_reg;
scan_inst->src[j].reg_offset =
diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
index 0c48dcd..5257094 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
@@ -53,9 +53,9 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t *block)
if (inst->opcode != BRW_OPCODE_MOV ||
!inst->saturate ||
- inst->dst.file != GRF ||
+ inst->dst.file != VGRF ||
inst->dst.type != inst->src[0].type ||
- inst->src[0].file != GRF ||
+ inst->src[0].file != VGRF ||
inst->src[0].abs ||
inst->src[0].negate)
continue;
@@ -90,7 +90,7 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t *block)
break;
}
for (int i = 0; i < scan_inst->sources; i++) {
- if (scan_inst->src[i].file == GRF &&
+ if (scan_inst->src[i].file == VGRF &&
scan_inst->src[i].nr == inst->src[0].nr &&
scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
if (scan_inst->opcode != BRW_OPCODE_MOV ||
diff --git a/src/mesa/drivers/dri/i965/brw_fs_validate.cpp b/src/mesa/drivers/dri/i965/brw_fs_validate.cpp
index a79c343..90edd02 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_validate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_validate.cpp
@@ -42,13 +42,13 @@ void
fs_visitor::validate()
{
foreach_block_and_inst (block, fs_inst, inst, cfg) {
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
fsv_assert(inst->dst.reg_offset + inst->regs_written <=
alloc.sizes[inst->dst.nr]);
}
for (unsigned i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
fsv_assert(inst->src[i].reg_offset + inst->regs_read(i) <=
(int)alloc.sizes[inst->src[i].nr]);
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index ef6e19a..e4f8bc5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -143,7 +143,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int coord_components,
* tracking to get the scaling factor.
*/
if (devinfo->gen < 6 && is_rect) {
- fs_reg dst = fs_reg(GRF, alloc.allocate(coord_components));
+ fs_reg dst = fs_reg(VGRF, alloc.allocate(coord_components));
fs_reg src = coordinate;
coordinate = dst;
@@ -578,7 +578,7 @@ fs_visitor::emit_interpolation_setup_gen6()
* Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
* compute our pixel centers.
*/
- fs_reg int_pixel_xy(GRF, alloc.allocate(dispatch_width / 8),
+ fs_reg int_pixel_xy(VGRF, alloc.allocate(dispatch_width / 8),
BRW_REGISTER_TYPE_UW);
const fs_builder dbld = abld.exec_all().group(dispatch_width * 2, 0);
@@ -905,7 +905,7 @@ fs_visitor::emit_urb_writes()
* "The write data payload can be between 1 and 8 message phases long."
*/
if (vue_map->slots_valid == 0) {
- fs_reg payload = fs_reg(GRF, alloc.allocate(2), BRW_REGISTER_TYPE_UD);
+ fs_reg payload = fs_reg(VGRF, alloc.allocate(2), BRW_REGISTER_TYPE_UD);
bld.exec_all().MOV(payload, fs_reg(retype(brw_vec8_grf(1, 0),
BRW_REGISTER_TYPE_UD)));
@@ -947,7 +947,7 @@ fs_visitor::emit_urb_writes()
break;
}
- fs_reg zero(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_reg zero(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
bld.MOV(zero, fs_reg(0u));
sources[length++] = zero;
@@ -999,7 +999,7 @@ fs_visitor::emit_urb_writes()
* temp register and use that for the payload.
*/
for (int i = 0; i < 4; i++) {
- fs_reg reg = fs_reg(GRF, alloc.allocate(1), outputs[varying].type);
+ fs_reg reg = fs_reg(VGRF, alloc.allocate(1), outputs[varying].type);
fs_reg src = offset(this->outputs[varying], bld, i);
set_saturate(true, bld.MOV(reg, src));
sources[length++] = reg;
@@ -1024,7 +1024,7 @@ fs_visitor::emit_urb_writes()
flush = true;
if (flush) {
fs_reg *payload_sources = ralloc_array(mem_ctx, fs_reg, length + 1);
- fs_reg payload = fs_reg(GRF, alloc.allocate(length + 1),
+ fs_reg payload = fs_reg(VGRF, alloc.allocate(length + 1),
BRW_REGISTER_TYPE_F);
payload_sources[0] =
fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
@@ -1057,7 +1057,7 @@ fs_visitor::emit_cs_terminate()
* make sure it uses the appropriate register range.
*/
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD);
- fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
bld.group(8, 0).exec_all().MOV(payload, g0);
/* Send a message to the thread spawner to terminate the thread. */
@@ -1074,7 +1074,7 @@ fs_visitor::emit_barrier()
/* We are getting the barrier ID from the compute shader header */
assert(stage == MESA_SHADER_COMPUTE);
- fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
const fs_builder pbld = bld.exec_all().group(8, 0);
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 9309ba5..a3b3a4f 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -90,7 +90,7 @@ byte_offset(fs_reg reg, unsigned delta)
switch (reg.file) {
case BAD_FILE:
break;
- case GRF:
+ case VGRF:
case ATTR:
reg.reg_offset += delta / 32;
break;
@@ -117,7 +117,7 @@ horiz_offset(fs_reg reg, unsigned delta)
* horizontal offset should be a harmless no-op.
*/
break;
- case GRF:
+ case VGRF:
case MRF:
case ATTR:
return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
@@ -159,7 +159,7 @@ half(fs_reg reg, unsigned idx)
case IMM:
return reg;
- case GRF:
+ case VGRF:
case MRF:
return horiz_offset(reg, 8 * idx);
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 236f74d..345c9c6 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -583,7 +583,7 @@ fs_instruction_scheduler::count_reads_remaining(backend_instruction *be)
if (is_src_duplicate(inst, i))
continue;
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]++;
} else if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
@@ -660,7 +660,7 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be)
if (!reads_remaining)
return;
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
written[inst->dst.nr] = true;
}
@@ -668,7 +668,7 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be)
if (is_src_duplicate(inst, i))
continue;
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]--;
} else if (inst->src[i].file == HW_REG &&
inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE &&
@@ -685,7 +685,7 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be)
fs_inst *inst = (fs_inst *)be;
int benefit = 0;
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
if (!BITSET_TEST(livein[block_idx], inst->dst.nr) &&
!written[inst->dst.nr])
benefit -= v->alloc.sizes[inst->dst.nr];
@@ -695,7 +695,7 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be)
if (is_src_duplicate(inst, i))
continue;
- if (inst->src[i].file == GRF &&
+ if (inst->src[i].file == VGRF &&
!BITSET_TEST(liveout[block_idx], inst->src[i].nr) &&
reads_remaining[inst->src[i].nr] == 1)
benefit += v->alloc.sizes[inst->src[i].nr];
@@ -951,7 +951,7 @@ fs_instruction_scheduler::calculate_deps()
/* read-after-write deps. */
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_read(i); r++)
add_dep(last_grf_write[inst->src[i].nr + r], n);
@@ -1003,7 +1003,7 @@ fs_instruction_scheduler::calculate_deps()
}
/* write-after-write deps. */
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_written; r++) {
add_dep(last_grf_write[inst->dst.nr + r], n);
@@ -1080,7 +1080,7 @@ fs_instruction_scheduler::calculate_deps()
/* write-after-read deps. */
for (int i = 0; i < inst->sources; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_read(i); r++)
add_dep(n, last_grf_write[inst->src[i].nr + r], 0);
@@ -1134,7 +1134,7 @@ fs_instruction_scheduler::calculate_deps()
/* Update the things this instruction wrote, so earlier reads
* can mark this as WAR dependency.
*/
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_written; r++)
last_grf_write[inst->dst.nr + r] = n;
@@ -1222,7 +1222,7 @@ vec4_instruction_scheduler::calculate_deps()
/* read-after-write deps. */
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(last_grf_write[inst->src[i].nr + j], n);
} else if (inst->src[i].file == HW_REG &&
@@ -1265,7 +1265,7 @@ vec4_instruction_scheduler::calculate_deps()
}
/* write-after-write deps. */
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
for (unsigned j = 0; j < inst->regs_written; ++j) {
add_dep(last_grf_write[inst->dst.nr + j], n);
last_grf_write[inst->dst.nr + j] = n;
@@ -1320,7 +1320,7 @@ vec4_instruction_scheduler::calculate_deps()
/* write-after-read deps. */
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(n, last_grf_write[inst->src[i].nr + j]);
} else if (inst->src[i].file == HW_REG &&
@@ -1361,7 +1361,7 @@ vec4_instruction_scheduler::calculate_deps()
/* Update the things this instruction wrote, so earlier reads
* can mark this as WAR dependency.
*/
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
for (unsigned j = 0; j < inst->regs_written; ++j)
last_grf_write[inst->dst.nr + j] = n;
} else if (inst->dst.file == MRF) {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 1c0d0cb..e6c63a9 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -39,7 +39,7 @@
#define MAX_VGRF_SIZE 16
enum PACKED register_file {
- GRF,
+ VGRF,
MRF,
IMM,
HW_REG, /* a struct brw_reg */
@@ -61,7 +61,7 @@ struct backend_reg : public brw_reg
bool is_accumulator() const;
bool in_range(const backend_reg &r, unsigned n) const;
- enum register_file file; /**< Register file: GRF, MRF, IMM. */
+ enum register_file file; /**< Register file: VGRF, MRF, IMM. */
/**
* Offset within the virtual register.
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index aa1aaf1..8672614 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -468,7 +468,7 @@ vec4_visitor::opt_reduce_swizzle()
/* Update sources' swizzles. */
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file != GRF &&
+ if (inst->src[i].file != VGRF &&
inst->src[i].file != ATTR &&
inst->src[i].file != UNIFORM)
continue;
@@ -913,7 +913,7 @@ vec4_visitor::opt_set_dependency_control()
*/
for (int i = 0; i < 3; i++) {
int reg = inst->src[i].nr + inst->src[i].reg_offset;
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
last_grf_write[reg] = NULL;
} else if (inst->src[i].file == HW_REG) {
memset(last_grf_write, 0, sizeof(last_grf_write));
@@ -932,7 +932,7 @@ vec4_visitor::opt_set_dependency_control()
* against a previous one writing to its destination.
*/
int reg = inst->dst.nr + inst->dst.reg_offset;
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
if (last_grf_write[reg] &&
!(inst->dst.writemask & grf_channels_written[reg])) {
last_grf_write[reg]->no_dd_clear = true;
@@ -1046,9 +1046,9 @@ vec4_visitor::opt_register_coalesce()
next_ip++;
if (inst->opcode != BRW_OPCODE_MOV ||
- (inst->dst.file != GRF && inst->dst.file != MRF) ||
+ (inst->dst.file != VGRF && inst->dst.file != MRF) ||
inst->predicate ||
- inst->src[0].file != GRF ||
+ inst->src[0].file != VGRF ||
inst->dst.type != inst->src[0].type ||
inst->src[0].abs || inst->src[0].negate || inst->src[0].reladdr)
continue;
@@ -1111,7 +1111,7 @@ vec4_visitor::opt_register_coalesce()
if (devinfo->gen == 6) {
/* gen6 math instructions must have the destination be
- * GRF, so no compute-to-MRF for them.
+ * VGRF, so no compute-to-MRF for them.
*/
if (scan_inst->is_math()) {
break;
@@ -1199,7 +1199,7 @@ vec4_visitor::opt_register_coalesce()
*/
vec4_instruction *scan_inst = _scan_inst;
while (scan_inst != inst) {
- if (scan_inst->dst.file == GRF &&
+ if (scan_inst->dst.file == VGRF &&
scan_inst->dst.nr == inst->src[0].nr &&
scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
scan_inst->reswizzle(inst->dst.writemask,
@@ -1302,11 +1302,11 @@ vec4_visitor::split_virtual_grfs()
* to split.
*/
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == GRF && inst->regs_written > 1)
+ if (inst->dst.file == VGRF && inst->regs_written > 1)
split_grf[inst->dst.nr] = false;
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF && inst->regs_read(i) > 1)
+ if (inst->src[i].file == VGRF && inst->regs_read(i) > 1)
split_grf[inst->src[i].nr] = false;
}
}
@@ -1328,14 +1328,14 @@ vec4_visitor::split_virtual_grfs()
}
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == GRF && split_grf[inst->dst.nr] &&
+ if (inst->dst.file == VGRF && split_grf[inst->dst.nr] &&
inst->dst.reg_offset != 0) {
inst->dst.nr = (new_virtual_grf[inst->dst.nr] +
inst->dst.reg_offset - 1);
inst->dst.reg_offset = 0;
}
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF && split_grf[inst->src[i].nr] &&
+ if (inst->src[i].file == VGRF && split_grf[inst->src[i].nr] &&
inst->src[i].reg_offset != 0) {
inst->src[i].nr = (new_virtual_grf[inst->src[i].nr] +
inst->src[i].reg_offset - 1);
@@ -1379,7 +1379,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
fprintf(file, " ");
switch (inst->dst.file) {
- case GRF:
+ case VGRF:
fprintf(file, "vgrf%d.%d", inst->dst.nr, inst->dst.reg_offset);
break;
case MRF:
@@ -1442,7 +1442,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
if (inst->src[i].abs)
fprintf(file, "|");
switch (inst->src[i].file) {
- case GRF:
+ case VGRF:
fprintf(file, "vgrf%d", inst->src[i].nr);
break;
case ATTR:
@@ -1510,7 +1510,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
/* Don't print .0; and only VGRFs have reg_offsets and sizes */
if (inst->src[i].reg_offset != 0 &&
- inst->src[i].file == GRF &&
+ inst->src[i].file == VGRF &&
alloc.sizes[inst->src[i].nr] != 1)
fprintf(file, ".%d", inst->src[i].reg_offset);
@@ -1783,7 +1783,7 @@ vec4_visitor::convert_to_hw_regs()
struct src_reg &src = inst->src[i];
struct brw_reg reg;
switch (src.file) {
- case GRF:
+ case VGRF:
reg = brw_vec8_grf(src.nr + src.reg_offset, 0);
reg.type = src.type;
reg.swizzle = src.swizzle;
@@ -1829,7 +1829,7 @@ vec4_visitor::convert_to_hw_regs()
struct brw_reg reg;
switch (inst->dst.file) {
- case GRF:
+ case VGRF:
reg = brw_vec8_grf(dst.nr + dst.reg_offset, 0);
reg.type = dst.type;
reg.writemask = dst.writemask;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_builder.h b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
index a90cadb..a76a4ce 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
@@ -144,7 +144,7 @@ namespace brw {
assert(dispatch_width() <= 32);
if (n > 0)
- return retype(dst_reg(GRF, shader->alloc.allocate(
+ return retype(dst_reg(VGRF, shader->alloc.allocate(
n * DIV_ROUND_UP(type_sz(type), 4))),
type);
else
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp
index 329f242..7aa8f5d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp
@@ -48,7 +48,7 @@ opt_cmod_propagation_local(bblock_t *block)
inst->opcode != BRW_OPCODE_MOV) ||
inst->predicate != BRW_PREDICATE_NONE ||
!inst->dst.is_null() ||
- inst->src[0].file != GRF ||
+ inst->src[0].file != VGRF ||
inst->src[0].abs)
continue;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index b986c12..3b76e36 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -47,7 +47,7 @@ is_direct_copy(vec4_instruction *inst)
{
return (inst->opcode == BRW_OPCODE_MOV &&
!inst->predicate &&
- inst->dst.file == GRF &&
+ inst->dst.file == VGRF &&
!inst->dst.reladdr &&
!inst->src[0].reladdr &&
(inst->dst.type == inst->src[0].type ||
@@ -70,8 +70,8 @@ is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
const src_reg *src = values[ch];
/* consider GRF only */
- assert(inst->dst.file == GRF);
- if (!src || src->file != GRF)
+ assert(inst->dst.file == VGRF);
+ if (!src || src->file != VGRF)
return false;
return (src->in_range(inst->dst, inst->regs_written) &&
@@ -292,7 +292,7 @@ try_copy_propagate(const struct brw_device_info *devinfo,
/* Check that we can propagate that value */
if (value.file != UNIFORM &&
- value.file != GRF &&
+ value.file != VGRF &&
value.file != ATTR)
return false;
@@ -416,14 +416,14 @@ vec4_visitor::opt_copy_propagation(bool do_constant_prop)
}
/* For each source arg, see if each component comes from a copy
- * from the same type file (IMM, GRF, UNIFORM), and try
+ * from the same type file (IMM, VGRF, UNIFORM), and try
* optimizing out access to the copy result
*/
for (int i = 2; i >= 0; i--) {
/* Copied values end up in GRFs, and we don't track reladdr
* accesses.
*/
- if (inst->src[i].file != GRF ||
+ if (inst->src[i].file != VGRF ||
inst->src[i].reladdr)
continue;
@@ -472,7 +472,7 @@ vec4_visitor::opt_copy_propagation(bool do_constant_prop)
}
/* Track available source registers. */
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
const int reg =
alloc.offsets[inst->dst.nr] + inst->dst.reg_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
index 259f604..cdb76e4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
@@ -174,7 +174,7 @@ vec4_visitor::opt_cse_local(bblock_t *block)
*/
bool no_existing_temp = entry->tmp.file == BAD_FILE;
if (no_existing_temp && !entry->generator->dst.is_null()) {
- entry->tmp = retype(src_reg(GRF, alloc.allocate(
+ entry->tmp = retype(src_reg(VGRF, alloc.allocate(
entry->generator->regs_written),
NULL), inst->dst.type);
@@ -242,7 +242,7 @@ vec4_visitor::opt_cse_local(bblock_t *block)
/* Kill any AEB entries using registers that don't get reused any
* more -- a sure sign they'll fail operands_match().
*/
- if (src->file == GRF) {
+ if (src->file == VGRF) {
if (var_range_end(var_from_reg(alloc, *src), 4) < ip) {
entry->remove();
ralloc_free(entry);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
index 284e0a8..20982cf 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
@@ -78,11 +78,11 @@ vec4_visitor::dead_code_eliminate()
sizeof(BITSET_WORD));
foreach_inst_in_block_reverse(vec4_instruction, inst, block) {
- if ((inst->dst.file == GRF && !inst->has_side_effects()) ||
+ if ((inst->dst.file == VGRF && !inst->has_side_effects()) ||
(inst->dst.is_null() && inst->writes_flag())){
bool result_live[4] = { false };
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
for (unsigned i = 0; i < inst->regs_written; i++) {
for (int c = 0; c < 4; c++)
result_live[c] |= BITSET_TEST(
@@ -134,7 +134,7 @@ vec4_visitor::dead_code_eliminate()
}
}
- if (inst->dst.file == GRF && !inst->predicate) {
+ if (inst->dst.file == VGRF && !inst->predicate) {
for (unsigned i = 0; i < inst->regs_written; i++) {
for (int c = 0; c < 4; c++) {
if (inst->dst.writemask & (1 << c)) {
@@ -151,7 +151,7 @@ vec4_visitor::dead_code_eliminate()
}
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); j++) {
for (int c = 0; c < 4; c++) {
BITSET_SET(live, var_from_reg(alloc,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
index aa9a657..57d5fbb 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
@@ -75,7 +75,7 @@ vec4_live_variables::setup_def_use()
/* Set use[] for this instruction */
for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); j++) {
for (int c = 0; c < 4; c++) {
const unsigned v =
@@ -97,7 +97,7 @@ vec4_live_variables::setup_def_use()
* are the things that screen off preceding definitions of a
* variable, and thus qualify for being in def[].
*/
- if (inst->dst.file == GRF &&
+ if (inst->dst.file == VGRF &&
(!inst->predicate || inst->opcode == BRW_OPCODE_SEL)) {
for (unsigned i = 0; i < inst->regs_written; i++) {
for (int c = 0; c < 4; c++) {
@@ -256,7 +256,7 @@ vec4_visitor::calculate_live_intervals()
int ip = 0;
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); j++) {
for (int c = 0; c < 4; c++) {
const unsigned v =
@@ -268,7 +268,7 @@ vec4_visitor::calculate_live_intervals()
}
}
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
for (unsigned i = 0; i < inst->regs_written; i++) {
for (int c = 0; c < 4; c++) {
if (inst->dst.writemask & (1 << c)) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
index 4aa98d7..12d281e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
@@ -82,7 +82,7 @@ inline unsigned
var_from_reg(const simple_allocator &alloc, const src_reg ®,
unsigned c = 0)
{
- assert(reg.file == GRF && reg.nr < alloc.count &&
+ assert(reg.file == VGRF && reg.nr < alloc.count &&
reg.reg_offset < alloc.sizes[reg.nr] && c < 4);
return (4 * (alloc.offsets[reg.nr] + reg.reg_offset) +
BRW_GET_SWZ(reg.swizzle, c));
@@ -92,7 +92,7 @@ inline unsigned
var_from_reg(const simple_allocator &alloc, const dst_reg ®,
unsigned c = 0)
{
- assert(reg.file == GRF && reg.nr < alloc.count &&
+ assert(reg.file == VGRF && reg.nr < alloc.count &&
reg.reg_offset < alloc.sizes[reg.nr] && c < 4);
return 4 * (alloc.offsets[reg.nr] + reg.reg_offset) + c;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index bdb3d02..f84a9f5 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -162,7 +162,7 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl)
unsigned array_elems =
reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
- nir_locals[reg->index] = dst_reg(GRF, alloc.allocate(array_elems));
+ nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(array_elems));
}
nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);
@@ -291,7 +291,7 @@ dst_reg
vec4_visitor::get_nir_dest(nir_dest dest)
{
if (dest.is_ssa) {
- dst_reg dst = dst_reg(GRF, alloc.allocate(1));
+ dst_reg dst = dst_reg(VGRF, alloc.allocate(1));
nir_ssa_values[dest.ssa.index] = dst;
return dst;
} else {
@@ -351,7 +351,7 @@ vec4_visitor::get_nir_src(nir_src src, unsigned num_components)
void
vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
{
- dst_reg reg = dst_reg(GRF, alloc.allocate(1));
+ dst_reg reg = dst_reg(VGRF, alloc.allocate(1));
reg.type = BRW_REGISTER_TYPE_D;
unsigned remaining = brw_writemask_for_size(instr->def.num_components);
@@ -1711,7 +1711,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
void
vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)
{
- nir_ssa_values[instr->def.index] = dst_reg(GRF, alloc.allocate(1));
+ nir_ssa_values[instr->def.index] = dst_reg(VGRF, alloc.allocate(1));
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index adad4e5..6d27a46 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -34,7 +34,7 @@ namespace brw {
static void
assign(unsigned int *reg_hw_locations, backend_reg *reg)
{
- if (reg->file == GRF) {
+ if (reg->file == VGRF) {
reg->nr = reg_hw_locations[reg->nr] + reg->reg_offset;
reg->reg_offset = 0;
}
@@ -55,11 +55,11 @@ vec4_visitor::reg_allocate_trivial()
}
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == GRF)
+ if (inst->dst.file == VGRF)
virtual_grf_used[inst->dst.nr] = true;
for (unsigned i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF)
+ if (inst->src[i].file == VGRF)
virtual_grf_used[inst->src[i].nr] = true;
}
}
@@ -292,12 +292,12 @@ static bool
can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
unsigned scratch_reg)
{
- assert(inst->src[i].file == GRF);
+ assert(inst->src[i].file == VGRF);
bool prev_inst_read_scratch_reg = false;
/* See if any previous source in the same instructions reads scratch_reg */
for (unsigned n = 0; n < i; n++) {
- if (inst->src[n].file == GRF && inst->src[n].nr == scratch_reg)
+ if (inst->src[n].file == VGRF && inst->src[n].nr == scratch_reg)
prev_inst_read_scratch_reg = true;
}
@@ -310,7 +310,7 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
* it if the write is not conditional and the channels we write are
* compatible with our read mask
*/
- if (prev_inst->dst.file == GRF && prev_inst->dst.nr == scratch_reg) {
+ if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) {
return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) &&
(brw_mask_for_swizzle(inst->src[i].swizzle) &
~prev_inst->dst.writemask) == 0;
@@ -329,7 +329,7 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
*/
int n;
for (n = 0; n < 3; n++) {
- if (prev_inst->src[n].file == GRF &&
+ if (prev_inst->src[n].file == VGRF &&
prev_inst->src[n].nr == scratch_reg) {
prev_inst_read_scratch_reg = true;
break;
@@ -374,7 +374,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
*/
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
+ if (inst->src[i].file == VGRF) {
/* We will only unspill src[i] it it wasn't unspilled for the
* previous instruction, in which case we'll just reuse the scratch
* reg for this instruction.
@@ -387,7 +387,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
}
}
- if (inst->dst.file == GRF) {
+ if (inst->dst.file == VGRF) {
spill_costs[inst->dst.nr] += loop_scale;
if (inst->dst.reladdr)
no_spill[inst->dst.nr] = true;
@@ -406,10 +406,10 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
case SHADER_OPCODE_GEN4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
for (int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF)
+ if (inst->src[i].file == VGRF)
no_spill[inst->src[i].nr] = true;
}
- if (inst->dst.file == GRF)
+ if (inst->dst.file == VGRF)
no_spill[inst->dst.nr] = true;
break;
@@ -445,7 +445,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
int scratch_reg = -1;
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF && inst->src[i].nr == spill_reg_nr) {
+ if (inst->src[i].file == VGRF && inst->src[i].nr == spill_reg_nr) {
if (scratch_reg == -1 ||
!can_use_scratch_for_source(inst, i, scratch_reg)) {
/* We need to unspill anyway so make sure we read the full vec4
@@ -465,7 +465,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
}
}
- if (inst->dst.file == GRF && inst->dst.nr == spill_reg_nr) {
+ if (inst->dst.file == VGRF && inst->dst.nr == spill_reg_nr) {
emit_scratch_write(block, inst, spill_offset);
scratch_reg = inst->dst.nr;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 48005b9..261ea84 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -632,7 +632,7 @@ src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type)
{
init();
- this->file = GRF;
+ this->file = VGRF;
this->nr = v->alloc.allocate(type_size_vec4(type));
if (type->is_array() || type->is_record()) {
@@ -650,7 +650,7 @@ src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type, int size)
init();
- this->file = GRF;
+ this->file = VGRF;
this->nr = v->alloc.allocate(type_size_vec4(type) * size);
this->swizzle = BRW_SWIZZLE_NOOP;
@@ -662,7 +662,7 @@ dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type)
{
init();
- this->file = GRF;
+ this->file = VGRF;
this->nr = v->alloc.allocate(type_size_vec4(type));
if (type->is_array() || type->is_record()) {
@@ -1632,7 +1632,7 @@ vec4_visitor::emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
*src.reladdr);
/* Now handle scratch access on src */
- if (src.file == GRF && scratch_loc[src.nr] != -1) {
+ if (src.file == VGRF && scratch_loc[src.nr] != -1) {
dst_reg temp = dst_reg(this, glsl_type::vec4_type);
emit_scratch_read(block, inst, temp, src, scratch_loc[src.nr]);
src.nr = temp.nr;
@@ -1660,7 +1660,7 @@ vec4_visitor::move_grf_array_access_to_scratch()
* scratch.
*/
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
- if (inst->dst.file == GRF && inst->dst.reladdr) {
+ if (inst->dst.file == VGRF && inst->dst.reladdr) {
if (scratch_loc[inst->dst.nr] == -1) {
scratch_loc[inst->dst.nr] = last_scratch;
last_scratch += this->alloc.sizes[inst->dst.nr];
@@ -1669,7 +1669,7 @@ vec4_visitor::move_grf_array_access_to_scratch()
for (src_reg *iter = inst->dst.reladdr;
iter->reladdr;
iter = iter->reladdr) {
- if (iter->file == GRF && scratch_loc[iter->nr] == -1) {
+ if (iter->file == VGRF && scratch_loc[iter->nr] == -1) {
scratch_loc[iter->nr] = last_scratch;
last_scratch += this->alloc.sizes[iter->nr];
}
@@ -1680,7 +1680,7 @@ vec4_visitor::move_grf_array_access_to_scratch()
for (src_reg *iter = &inst->src[i];
iter->reladdr;
iter = iter->reladdr) {
- if (iter->file == GRF && scratch_loc[iter->nr] == -1) {
+ if (iter->file == VGRF && scratch_loc[iter->nr] == -1) {
scratch_loc[iter->nr] = last_scratch;
last_scratch += this->alloc.sizes[iter->nr];
}
@@ -1708,7 +1708,7 @@ vec4_visitor::move_grf_array_access_to_scratch()
/* Now that we have handled any (possibly recursive) reladdr scratch
* accesses for dst we can safely do the scratch write for dst itself
*/
- if (inst->dst.file == GRF && scratch_loc[inst->dst.nr] != -1)
+ if (inst->dst.file == VGRF && scratch_loc[inst->dst.nr] != -1)
emit_scratch_write(block, inst, scratch_loc[inst->dst.nr]);
/* Now handle scratch access on any src. In this case, since inst->src[i]
--
2.4.9
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