[Mesa-dev] [PATCH 18/24] i965: Combine register file field.
Matt Turner
mattst88 at gmail.com
Mon Nov 2 16:29:28 PST 2015
The first four values (2-bits) are hardware values, and VGRF, ATTR, and
UNIFORM remain values used in the IR.
---
src/mesa/drivers/dri/i965/brw_defines.h | 11 +++++++++++
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 ++---
src/mesa/drivers/dri/i965/brw_ir_fs.h | 4 ++--
src/mesa/drivers/dri/i965/brw_ir_vec4.h | 8 ++++----
src/mesa/drivers/dri/i965/brw_reg.h | 4 ++--
src/mesa/drivers/dri/i965/brw_shader.h | 13 -------------
src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 +++++-----
7 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 00464e2..5ab77bc 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1376,6 +1376,17 @@ enum PACKED brw_reg_file {
BRW_GENERAL_REGISTER_FILE = 1,
BRW_MESSAGE_REGISTER_FILE = 2,
BRW_IMMEDIATE_VALUE = 3,
+
+ ARF = BRW_ARCHITECTURE_REGISTER_FILE,
+ GRF = BRW_GENERAL_REGISTER_FILE,
+ MRF = BRW_MESSAGE_REGISTER_FILE,
+ IMM = BRW_IMMEDIATE_VALUE,
+
+ /* These are not hardware values */
+ VGRF,
+ ATTR,
+ UNIFORM, /* prog_data->params[reg] */
+ BAD_FILE,
};
#define BRW_HW_REG_TYPE_UD 0
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 6eeafd5..3d2b051 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -423,7 +423,6 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
fs_reg::fs_reg(struct brw_reg reg) :
backend_reg(reg)
{
- this->file = (enum register_file)reg.file;
this->reg_offset = 0;
this->subreg_offset = 0;
this->reladdr = NULL;
@@ -940,7 +939,7 @@ fs_visitor::vgrf(const glsl_type *const type)
brw_type_for_base_type(type));
}
-fs_reg::fs_reg(enum register_file file, int nr)
+fs_reg::fs_reg(enum brw_reg_file file, int nr)
{
init();
this->file = file;
@@ -949,7 +948,7 @@ fs_reg::fs_reg(enum register_file file, int nr)
this->stride = (file == UNIFORM ? 0 : 1);
}
-fs_reg::fs_reg(enum register_file file, int nr, enum brw_reg_type type)
+fs_reg::fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type)
{
init();
this->file = file;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 3d038f8..d38764e 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -42,8 +42,8 @@ public:
explicit fs_reg(uint8_t vf[4]);
explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
fs_reg(struct brw_reg reg);
- fs_reg(enum register_file file, int nr);
- fs_reg(enum register_file file, int nr, enum brw_reg_type type);
+ fs_reg(enum brw_reg_file file, int nr);
+ fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
bool equals(const fs_reg &r) const;
bool is_contiguous() const;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index f6c7595..096825d 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -39,7 +39,7 @@ public:
void init();
- src_reg(register_file file, int nr, const glsl_type *type);
+ src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
src_reg();
src_reg(float f);
src_reg(uint32_t u);
@@ -108,10 +108,10 @@ public:
void init();
dst_reg();
- dst_reg(register_file file, int nr);
- dst_reg(register_file file, int nr, const glsl_type *type,
+ dst_reg(enum brw_reg_file file, int nr);
+ dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
unsigned writemask);
- dst_reg(register_file file, int nr, brw_reg_type type,
+ dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
unsigned writemask);
dst_reg(struct brw_reg reg);
dst_reg(class vec4_visitor *v, const struct glsl_type *type);
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h
index d86c746..b906892 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -232,11 +232,11 @@ const char *brw_reg_type_letters(unsigned brw_reg_type);
*/
struct brw_reg {
enum brw_reg_type type:4;
- enum brw_reg_file file:2;
+ enum brw_reg_file file:3; /* :2 hardware format */
unsigned negate:1; /* source only */
unsigned abs:1; /* source only */
unsigned address_mode:1; /* relative addressing, hopefully! */
- unsigned pad0:2;
+ unsigned pad0:1;
unsigned subnr:5; /* :1 in align16 */
unsigned nr:16;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index a59c953..31172a8 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -38,17 +38,6 @@
#define MAX_SAMPLER_MESSAGE_SIZE 11
#define MAX_VGRF_SIZE 16
-enum PACKED register_file {
- ARF,
- GRF,
- MRF,
- IMM,
- VGRF,
- ATTR,
- UNIFORM, /* prog_data->params[reg] */
- BAD_FILE,
-};
-
#ifdef __cplusplus
struct backend_reg : public brw_reg
{
@@ -62,8 +51,6 @@ struct backend_reg : public brw_reg
bool is_accumulator() const;
bool in_range(const backend_reg &r, unsigned n) const;
- enum register_file file; /**< Register file: VGRF, MRF, IMM. */
-
/**
* Offset within the virtual register.
*
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index bb5c7ac..928ba74 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -51,7 +51,7 @@ src_reg::init()
this->file = BAD_FILE;
}
-src_reg::src_reg(register_file file, int nr, const glsl_type *type)
+src_reg::src_reg(enum brw_reg_file file, int nr, const glsl_type *type)
{
init();
@@ -147,7 +147,7 @@ dst_reg::dst_reg()
init();
}
-dst_reg::dst_reg(register_file file, int nr)
+dst_reg::dst_reg(enum brw_reg_file file, int nr)
{
init();
@@ -155,7 +155,7 @@ dst_reg::dst_reg(register_file file, int nr)
this->nr = nr;
}
-dst_reg::dst_reg(register_file file, int nr, const glsl_type *type,
+dst_reg::dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
unsigned writemask)
{
init();
@@ -166,7 +166,7 @@ dst_reg::dst_reg(register_file file, int nr, const glsl_type *type,
this->writemask = writemask;
}
-dst_reg::dst_reg(register_file file, int nr, brw_reg_type type,
+dst_reg::dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
unsigned writemask)
{
init();
@@ -346,7 +346,7 @@ vec4_visitor::opt_vector_float()
bool progress = false;
int last_reg = -1, last_reg_offset = -1;
- enum register_file last_reg_file = BAD_FILE;
+ enum brw_reg_file last_reg_file = BAD_FILE;
int remaining_channels = 0;
uint8_t imm[4];
--
2.4.9
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