[Mesa-dev] [RFC 3/5] i965/fs: Plumb separate surfaces and samplers through from NIR
Jason Ekstrand
jason at jlekstrand.net
Tue Nov 3 13:26:02 PST 2015
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 47 +++++++++++++++----------
src/mesa/drivers/dri/i965/brw_fs.h | 4 ++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 25 +++++++++----
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16 +++++----
6 files changed, 60 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 5308d17..7fa4ce8 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -85,7 +85,7 @@ brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
unsigned msg_length)
{
fs_inst *inst = new (mem_ctx) fs_inst(op, 16, dst, brw_message_reg(base_mrf),
- fs_reg(0u));
+ fs_reg(0u), fs_reg(0u));
inst->base_mrf = base_mrf;
inst->mlen = msg_length;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 2d0acb9..92fa02f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -723,15 +723,15 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
- assert(src[8].file == IMM && src[9].file == IMM);
+ assert(src[9].file == IMM && src[10].file == IMM);
/* Texture coordinates. */
if (i == 0)
- return src[8].fixed_hw_reg.dw1.ud;
+ return src[9].fixed_hw_reg.dw1.ud;
/* Texture derivatives. */
else if ((i == 2 || i == 3) && opcode == SHADER_OPCODE_TXD_LOGICAL)
- return src[9].fixed_hw_reg.dw1.ud;
+ return src[10].fixed_hw_reg.dw1.ud;
/* Texture offset. */
- else if (i == 7)
+ else if (i == 8)
return 2;
else
return 1;
@@ -3505,6 +3505,7 @@ lower_sampler_logical_send_gen4(const fs_builder &bld, fs_inst *inst, opcode op,
const fs_reg &coordinate,
const fs_reg &shadow_c,
const fs_reg &lod, const fs_reg &lod2,
+ const fs_reg &surface,
const fs_reg &sampler,
unsigned coord_components,
unsigned grad_components)
@@ -3597,8 +3598,9 @@ lower_sampler_logical_send_gen4(const fs_builder &bld, fs_inst *inst, opcode op,
inst->opcode = op;
inst->src[0] = reg_undef;
- inst->src[1] = sampler;
- inst->resize_sources(2);
+ inst->src[1] = surface;
+ inst->src[2] = sampler;
+ inst->resize_sources(3);
inst->base_mrf = msg_begin.reg;
inst->mlen = msg_end.reg - msg_begin.reg;
inst->header_size = 1;
@@ -3610,6 +3612,7 @@ lower_sampler_logical_send_gen5(const fs_builder &bld, fs_inst *inst, opcode op,
const fs_reg &shadow_c,
fs_reg lod, fs_reg lod2,
const fs_reg &sample_index,
+ const fs_reg &surface,
const fs_reg &sampler,
const fs_reg &offset_value,
unsigned coord_components,
@@ -3692,8 +3695,9 @@ lower_sampler_logical_send_gen5(const fs_builder &bld, fs_inst *inst, opcode op,
inst->opcode = op;
inst->src[0] = reg_undef;
- inst->src[1] = sampler;
- inst->resize_sources(2);
+ inst->src[1] = surface;
+ inst->src[2] = sampler;
+ inst->resize_sources(3);
inst->base_mrf = message.reg;
inst->mlen = msg_end.reg - message.reg;
inst->header_size = header_size;
@@ -3717,7 +3721,9 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
const fs_reg &shadow_c,
fs_reg lod, fs_reg lod2,
const fs_reg &sample_index,
- const fs_reg &mcs, const fs_reg &sampler,
+ const fs_reg &mcs,
+ const fs_reg &surface,
+ const fs_reg &sampler,
fs_reg offset_value,
unsigned coord_components,
unsigned grad_components)
@@ -3906,8 +3912,9 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
/* Generate the SEND. */
inst->opcode = op;
inst->src[0] = src_payload;
- inst->src[1] = sampler;
- inst->resize_sources(2);
+ inst->src[1] = surface;
+ inst->src[2] = sampler;
+ inst->resize_sources(3);
inst->base_mrf = -1;
inst->mlen = mlen;
inst->header_size = header_size;
@@ -3926,25 +3933,27 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
const fs_reg &lod2 = inst->src[3];
const fs_reg &sample_index = inst->src[4];
const fs_reg &mcs = inst->src[5];
- const fs_reg &sampler = inst->src[6];
- const fs_reg &offset_value = inst->src[7];
- assert(inst->src[8].file == IMM && inst->src[9].file == IMM);
- const unsigned coord_components = inst->src[8].fixed_hw_reg.dw1.ud;
- const unsigned grad_components = inst->src[9].fixed_hw_reg.dw1.ud;
+ const fs_reg &surface = inst->src[6];
+ const fs_reg &sampler = inst->src[7];
+ const fs_reg &offset_value = inst->src[8];
+ assert(inst->src[9].file == IMM && inst->src[10].file == IMM);
+ const unsigned coord_components = inst->src[9].fixed_hw_reg.dw1.ud;
+ const unsigned grad_components = inst->src[10].fixed_hw_reg.dw1.ud;
if (devinfo->gen >= 7) {
lower_sampler_logical_send_gen7(bld, inst, op, coordinate,
shadow_c, lod, lod2, sample_index,
- mcs, sampler, offset_value,
+ mcs, surface, sampler, offset_value,
coord_components, grad_components);
} else if (devinfo->gen >= 5) {
lower_sampler_logical_send_gen5(bld, inst, op, coordinate,
shadow_c, lod, lod2, sample_index,
- sampler, offset_value,
+ surface, sampler, offset_value,
coord_components, grad_components);
} else {
lower_sampler_logical_send_gen4(bld, inst, op, coordinate,
- shadow_c, lod, lod2, sampler,
+ shadow_c, lod, lod2,
+ surface, sampler,
coord_components, grad_components);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index b06a069..ec38693 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -114,7 +114,7 @@ public:
void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
void compute_clip_distance(gl_clip_plane *clip_planes);
- uint32_t gather_channel(int orig_chan, uint32_t sampler);
+ uint32_t gather_channel(int orig_chan, uint32_t surface, uint32_t sampler);
void swizzle_result(ir_texture_opcode op, int dest_components,
fs_reg orig_val, uint32_t sampler);
@@ -225,6 +225,8 @@ public:
int gather_component,
bool is_cube_array,
bool is_rect,
+ uint32_t surface,
+ fs_reg surface_reg,
uint32_t sampler,
fs_reg sampler_reg);
fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 14a8f29..d1a4dc4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -2061,7 +2061,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
- generate_tex(inst, dst, src[0], src[1], src[1]);
+ generate_tex(inst, dst, src[0], src[1], src[2]);
break;
case FS_OPCODE_DDX_COARSE:
case FS_OPCODE_DDX_FINE:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 81cabaf..db859c3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1984,7 +1984,9 @@ fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld,
void
fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
{
+ unsigned texture = instr->texture_index;
unsigned sampler = instr->sampler_index;
+ fs_reg texture_reg(texture);
fs_reg sampler_reg(sampler);
int gather_component = instr->component;
@@ -2052,9 +2054,9 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
case nir_tex_src_projector:
unreachable("should be lowered");
- case nir_tex_src_sampler_offset: {
- /* Figure out the highest possible sampler index and mark it as used */
- uint32_t max_used = sampler + instr->texture_array_size - 1;
+ case nir_tex_src_texture_offset: {
+ /* Figure out the highest possible texture index and mark it as used */
+ uint32_t max_used = texture + instr->texture_array_size - 1;
if (instr->op == nir_texop_tg4 && devinfo->gen < 8) {
max_used += stage_prog_data->binding_table.gather_texture_start;
} else {
@@ -2063,6 +2065,14 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
brw_mark_surface_used(prog_data, max_used);
/* Emit code to evaluate the actual indexing expression */
+ texture_reg = vgrf(glsl_type::uint_type);
+ bld.ADD(texture_reg, src, fs_reg(texture));
+ texture_reg = bld.emit_uniformize(texture_reg);
+ break;
+ }
+
+ case nir_tex_src_sampler_offset: {
+ /* Emit code to evaluate the actual indexing expression */
sampler_reg = vgrf(glsl_type::uint_type);
bld.ADD(sampler_reg, src, fs_reg(sampler));
sampler_reg = bld.emit_uniformize(sampler_reg);
@@ -2076,8 +2086,8 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
if (instr->op == nir_texop_txf_ms) {
if (devinfo->gen >= 7 &&
- key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
- mcs = emit_mcs_fetch(coordinate, instr->coord_components, sampler_reg);
+ key_tex->compressed_multisample_layout_mask & (1 << texture)) {
+ mcs = emit_mcs_fetch(coordinate, instr->coord_components, texture_reg);
} else {
mcs = fs_reg(0u);
}
@@ -2114,7 +2124,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D);
fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, dst,
bld.vgrf(BRW_REGISTER_TYPE_D, 1),
- sampler_reg);
+ texture_reg, texture_reg);
inst->mlen = 1;
inst->header_size = 1;
inst->base_mrf = -1;
@@ -2127,7 +2137,8 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
emit_texture(op, dest_type, coordinate, instr->coord_components,
shadow_comparitor, lod, lod2, lod_components, sample_index,
tex_offset, mcs, gather_component,
- is_cube_array, is_rect, sampler, sampler_reg);
+ is_cube_array, is_rect,
+ texture, texture_reg, sampler, sampler_reg);
fs_reg dest = get_nir_dest(instr->dest);
dest.type = this->result.type;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 5c57944..ab0ba75 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -198,12 +198,12 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int coord_components,
/* Sample from the MCS surface attached to this multisample texture. */
fs_reg
fs_visitor::emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
- const fs_reg &sampler)
+ const fs_reg &texture)
{
const fs_reg dest = vgrf(glsl_type::uvec4_type);
const fs_reg srcs[] = {
coordinate, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
- sampler, fs_reg(), fs_reg(components), fs_reg(0)
+ texture, texture, fs_reg(), fs_reg(components), fs_reg(0)
};
fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs,
ARRAY_SIZE(srcs));
@@ -228,6 +228,8 @@ fs_visitor::emit_texture(ir_texture_opcode op,
int gather_component,
bool is_cube_array,
bool is_rect,
+ uint32_t surface,
+ fs_reg surface_reg,
uint32_t sampler,
fs_reg sampler_reg)
{
@@ -273,7 +275,7 @@ fs_visitor::emit_texture(ir_texture_opcode op,
fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1));
const fs_reg srcs[] = {
coordinate, shadow_c, lod, lod2,
- sample_index, mcs, sampler_reg, offset_value,
+ sample_index, mcs, surface_reg, sampler_reg, offset_value,
fs_reg(coord_components), fs_reg(grad_components)
};
enum opcode opcode;
@@ -323,10 +325,10 @@ fs_visitor::emit_texture(ir_texture_opcode op,
if (op == ir_tg4) {
inst->offset |=
- gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
+ gather_channel(gather_component, surface, sampler) << 16; /* M0.2:16-17 */
if (devinfo->gen == 6)
- emit_gen6_gather_wa(key_tex->gen6_gather_wa[sampler], dst);
+ emit_gen6_gather_wa(key_tex->gen6_gather_wa[surface], dst);
}
/* fixup #layers for cube map arrays */
@@ -384,7 +386,7 @@ fs_visitor::emit_gen6_gather_wa(uint8_t wa, fs_reg dst)
* Set up the gather channel based on the swizzle, for gather4.
*/
uint32_t
-fs_visitor::gather_channel(int orig_chan, uint32_t sampler)
+fs_visitor::gather_channel(int orig_chan, uint32_t surface, uint32_t sampler)
{
int swiz = GET_SWZ(key_tex->swizzles[sampler], orig_chan);
switch (swiz) {
@@ -393,7 +395,7 @@ fs_visitor::gather_channel(int orig_chan, uint32_t sampler)
/* gather4 sampler is broken for green channel on RG32F --
* we must ask for blue instead.
*/
- if (key_tex->gather_channel_quirk_mask & (1 << sampler))
+ if (key_tex->gather_channel_quirk_mask & (1 << surface))
return 2;
return 1;
case SWIZZLE_Z: return 2;
--
2.5.0.400.gff86faf
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