[Mesa-dev] [PATCH 1/7] i965: use real latencies in the pre-RA scheduler

[Jason Ekstrand]

On Fri, Oct 30, 2015 at 6:02 PM, Connor Abbott <cwabbott0 at gmail.com> wrote:
> Before, we simply assumed that reducing register pressure was the number
> one priority in the pre-RA scheduler, and set the latency of every
> instruction to 1 to get the scheduler to ignore it. But for the
> aggressive scheduler, this doesn't make much sense. It can also allow
> the register allocator to introduce additional false dependencies that
> disallowing us from putting instructions in a better order, when we
> could avoid the whole thing by putting them in that order in the first
> place. The only issue that this causes is that we may fall back to the
> register pressure scheduler, which is even worse for latencies, by
> making the first schedule more aggressive, but soon we'll switching to
> that strategy dynamically based on register pressure anyways, at which
> point making the latencies only 1 makes no sense at all.
>
> total instructions in shared programs: 7440130 -> 7447753 (0.10%)
> instructions in affected programs: 32614 -> 40237 (23.37%)
> helped: 4
> HURT: 26
>
> total cycles in shared programs: 56282914 -> 52733940 (-6.31%)
> cycles in affected programs: 34510450 -> 30961476 (-10.28%)
> helped: 23664
> HURT: 3343

So, I ran the benchmarks and, rather surprisingly, this is the only
patch in the series which overwhelmingly helps.

In particular, it helps heaven by 4.5%, trex by a little under 1%, and
helps one of the synthetics by 125%.  I'm having a little trouble
believing that second number but it seems more-or-less legit. I
haven't looked at it in detail (ShMapPcf if you're wondering).

The stuff between this patch and bottom-up (inclusive) is more-or-less
a wash with the above mentioned synthetic being hurt pretty bad.
Also, there's a bug somewhere because heaven misrenders on HSW pretty
bad with the full series (I haven't bisected).

This patch is

Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>


> LOST:   257
> GAINED: 35
> Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
> ---
>  src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> index 2698399..a611dd1 100644
> --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> @@ -777,9 +777,7 @@ schedule_node::schedule_node(backend_instruction *inst,
>     /* We can't measure Gen6 timings directly but expect them to be much
>      * closer to Gen7 than Gen4.
>      */
> -   if (!sched->post_reg_alloc)
> -      this->latency = 1;
> -   else if (devinfo->gen >= 6)
> +   if (devinfo->gen >= 6)
>        set_latency_gen7(devinfo->is_haswell);
>     else
>        set_latency_gen4();
> --
> 2.4.3
>
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