[Mesa-dev] [PATCH 01/36] i965: Define symbolic constants for some useful L3 cache control registers.

[Jordan Justen]

Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

On 2015-11-14 13:43:37, Jordan Justen wrote:
> From: Francisco Jerez <currojerez at riseup.net>
> 
> ---
>  src/mesa/drivers/dri/i965/intel_reg.h | 53 +++++++++++++++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
> index a261c2b..0b167d5 100644
> --- a/src/mesa/drivers/dri/i965/intel_reg.h
> +++ b/src/mesa/drivers/dri/i965/intel_reg.h
> @@ -192,3 +192,56 @@
>  #define MI_PREDICATE_RESULT             0x2418
>  #define MI_PREDICATE_RESULT_1           0x241C
>  #define MI_PREDICATE_RESULT_2           0x2214
> +
> +/* L3 cache control registers. */
> +#define GEN7_L3SQCREG1                     0xb010
> +/* L3SQ general and high priority credit initialization. */
> +# define IVB_L3SQCREG1_SQGHPCI_DEFAULT     0x00730000
> +# define VLV_L3SQCREG1_SQGHPCI_DEFAULT     0x00d30000
> +# define HSW_L3SQCREG1_SQGHPCI_DEFAULT     0x00610000
> +# define GEN7_L3SQCREG1_CONV_DC_UC         (1 << 24)
> +# define GEN7_L3SQCREG1_CONV_IS_UC         (1 << 25)
> +# define GEN7_L3SQCREG1_CONV_C_UC          (1 << 26)
> +# define GEN7_L3SQCREG1_CONV_T_UC          (1 << 27)
> +
> +#define GEN7_L3CNTLREG2                    0xb020
> +# define GEN7_L3CNTLREG2_SLM_ENABLE        (1 << 0)
> +# define GEN7_L3CNTLREG2_URB_ALLOC_SHIFT   1
> +# define GEN7_L3CNTLREG2_URB_ALLOC_MASK    INTEL_MASK(6, 1)
> +# define GEN7_L3CNTLREG2_URB_LOW_BW        (1 << 7)
> +# define GEN7_L3CNTLREG2_ALL_ALLOC_SHIFT   8
> +# define GEN7_L3CNTLREG2_ALL_ALLOC_MASK    INTEL_MASK(13, 8)
> +# define GEN7_L3CNTLREG2_RO_ALLOC_SHIFT    14
> +# define GEN7_L3CNTLREG2_RO_ALLOC_MASK     INTEL_MASK(19, 14)
> +# define GEN7_L3CNTLREG2_RO_LOW_BW         (1 << 20)
> +# define GEN7_L3CNTLREG2_DC_ALLOC_SHIFT    21
> +# define GEN7_L3CNTLREG2_DC_ALLOC_MASK     INTEL_MASK(26, 21)
> +# define GEN7_L3CNTLREG2_DC_LOW_BW         (1 << 27)
> +
> +#define GEN7_L3CNTLREG3                    0xb024
> +# define GEN7_L3CNTLREG3_IS_ALLOC_SHIFT    1
> +# define GEN7_L3CNTLREG3_IS_ALLOC_MASK     INTEL_MASK(6, 1)
> +# define GEN7_L3CNTLREG3_IS_LOW_BW         (1 << 7)
> +# define GEN7_L3CNTLREG3_C_ALLOC_SHIFT     8
> +# define GEN7_L3CNTLREG3_C_ALLOC_MASK      INTEL_MASK(13, 8)
> +# define GEN7_L3CNTLREG3_C_LOW_BW          (1 << 14)
> +# define GEN7_L3CNTLREG3_T_ALLOC_SHIFT     15
> +# define GEN7_L3CNTLREG3_T_ALLOC_MASK      INTEL_MASK(20, 15)
> +# define GEN7_L3CNTLREG3_T_LOW_BW          (1 << 21)
> +
> +#define HSW_SCRATCH1                       0xb038
> +#define HSW_SCRATCH1_L3_ATOMIC_DISABLE     (1 << 27)
> +
> +#define HSW_ROW_CHICKEN3                   0xe49c
> +#define HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE (1 << 6)
> +
> +#define GEN8_L3CNTLREG                     0x7034
> +# define GEN8_L3CNTLREG_SLM_ENABLE         (1 << 0)
> +# define GEN8_L3CNTLREG_URB_ALLOC_SHIFT    1
> +# define GEN8_L3CNTLREG_URB_ALLOC_MASK     INTEL_MASK(7, 1)
> +# define GEN8_L3CNTLREG_RO_ALLOC_SHIFT     11
> +# define GEN8_L3CNTLREG_RO_ALLOC_MASK      INTEL_MASK(17, 11)
> +# define GEN8_L3CNTLREG_DC_ALLOC_SHIFT     18
> +# define GEN8_L3CNTLREG_DC_ALLOC_MASK      INTEL_MASK(24, 18)
> +# define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT    25
> +# define GEN8_L3CNTLREG_ALL_ALLOC_MASK     INTEL_MASK(31, 25)
> -- 
> 2.6.2
> 
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