[Mesa-dev] [PATCH] radeonsi: use proper GRBM_GFX_INDEX offset for CI+
Marek Olšák
maraeo at gmail.com
Mon Nov 16 02:30:08 PST 2015
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Marek
On Fri, Nov 13, 2015 at 10:22 PM, Alex Deucher <alexdeucher at gmail.com> wrote:
> The offset is different on CI and newer.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> src/gallium/drivers/radeonsi/si_state.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index ff4d612..14763f7 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3259,21 +3259,29 @@ si_write_harvested_raster_configs(struct si_context *sctx,
> }
> }
>
> - /* GRBM_GFX_INDEX is privileged on VI */
> - if (sctx->b.chip_class <= CIK)
> + /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
> + if (sctx->b.chip_class < CIK)
> si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
> SE_INDEX(se) | SH_BROADCAST_WRITES |
> INSTANCE_BROADCAST_WRITES);
> + else
> + si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
> + S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
> + S_030800_INSTANCE_BROADCAST_WRITES(1));
> si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
> if (sctx->b.chip_class >= CIK)
> si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
> }
>
> - /* GRBM_GFX_INDEX is privileged on VI */
> - if (sctx->b.chip_class <= CIK)
> + /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
> + if (sctx->b.chip_class < CIK)
> si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
> SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
> INSTANCE_BROADCAST_WRITES);
> + else
> + si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
> + S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
> + S_030800_INSTANCE_BROADCAST_WRITES(1));
> }
>
> static void si_init_config(struct si_context *sctx)
> --
> 1.8.3.1
>
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