[Mesa-dev] [PATCH 1/2] i965: Convert scalar_* flags to a scalar_stage array.
Jordan Justen
jordan.l.justen at intel.com
Mon Nov 16 11:39:24 PST 2015
On 2015-11-12 15:38:51, Kenneth Graunke wrote:
> I was going to add scalar_tcs and scalar_tes flags, and then thought
> better of it and decided to convert this to an array. Simpler.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
> src/mesa/drivers/dri/i965/brw_compiler.h | 3 +--
> src/mesa/drivers/dri/i965/brw_context.c | 2 +-
> src/mesa/drivers/dri/i965/brw_gs.c | 3 ++-
> src/mesa/drivers/dri/i965/brw_link.cpp | 11 +++++---
> src/mesa/drivers/dri/i965/brw_program.c | 3 ++-
> src/mesa/drivers/dri/i965/brw_shader.cpp | 31 ++++++-----------------
> src/mesa/drivers/dri/i965/brw_shader.h | 2 --
> src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 +--
> src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_vs.c | 7 ++---
> 10 files changed, 28 insertions(+), 40 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
> index e3a26d6..3f54616 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.h
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.h
> @@ -89,8 +89,7 @@ struct brw_compiler {
> void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
> void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
>
> - bool scalar_vs;
> - bool scalar_gs;
> + bool scalar_stage[MESA_SHADER_STAGES];
> struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
> };
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index ac6045d..2db99c7 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -525,7 +525,7 @@ brw_initialize_context_constants(struct brw_context *brw)
> ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxImageUniforms =
> BRW_MAX_IMAGES;
> ctx->Const.Program[MESA_SHADER_VERTEX].MaxImageUniforms =
> - (brw->intelScreen->compiler->scalar_vs ? BRW_MAX_IMAGES : 0);
> + (brw->intelScreen->compiler->scalar_stage[MESA_SHADER_VERTEX] ? BRW_MAX_IMAGES : 0);
Line > 80.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
> ctx->Const.Program[MESA_SHADER_COMPUTE].MaxImageUniforms =
> BRW_MAX_IMAGES;
> ctx->Const.MaxImageUnits = MAX_IMAGE_UNITS;
> diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
> index ed0890f..ad5b242 100644
> --- a/src/mesa/drivers/dri/i965/brw_gs.c
> +++ b/src/mesa/drivers/dri/i965/brw_gs.c
> @@ -87,7 +87,8 @@ brw_codegen_gs_prog(struct brw_context *brw,
> prog_data.base.base.nr_image_params = gs->NumImages;
>
> brw_nir_setup_glsl_uniforms(gp->program.Base.nir, prog, &gp->program.Base,
> - &prog_data.base.base, compiler->scalar_gs);
> + &prog_data.base.base,
> + compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
>
> GLbitfield64 outputs_written = gp->program.Base.OutputsWritten;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
> index 2991173..14421d4 100644
> --- a/src/mesa/drivers/dri/i965/brw_link.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_link.cpp
> @@ -66,12 +66,14 @@ brw_lower_packing_builtins(struct brw_context *brw,
> gl_shader_stage shader_type,
> exec_list *ir)
> {
> + const struct brw_compiler *compiler = brw->intelScreen->compiler;
> +
> int ops = LOWER_PACK_SNORM_2x16
> | LOWER_UNPACK_SNORM_2x16
> | LOWER_PACK_UNORM_2x16
> | LOWER_UNPACK_UNORM_2x16;
>
> - if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
> + if (compiler->scalar_stage[shader_type]) {
> ops |= LOWER_UNPACK_UNORM_4x8
> | LOWER_UNPACK_SNORM_4x8
> | LOWER_PACK_UNORM_4x8
> @@ -84,7 +86,7 @@ brw_lower_packing_builtins(struct brw_context *brw,
> * lowering is needed. For SOA code, the Half2x16 ops must be
> * scalarized.
> */
> - if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
> + if (compiler->scalar_stage[shader_type]) {
> ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
> | LOWER_UNPACK_HALF_2x16_TO_SPLIT;
> }
> @@ -103,6 +105,7 @@ process_glsl_ir(gl_shader_stage stage,
> struct gl_shader *shader)
> {
> struct gl_context *ctx = &brw->ctx;
> + const struct brw_compiler *compiler = brw->intelScreen->compiler;
> const struct gl_shader_compiler_options *options =
> &ctx->Const.ShaderCompilerOptions[shader->Stage];
>
> @@ -161,7 +164,7 @@ process_glsl_ir(gl_shader_stage stage,
> do {
> progress = false;
>
> - if (is_scalar_shader_stage(brw->intelScreen->compiler, shader->Stage)) {
> + if (compiler->scalar_stage[shader->Stage]) {
> brw_do_channel_expressions(shader->ir);
> brw_do_vector_splitting(shader->ir);
> }
> @@ -252,7 +255,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
> brw_add_texrect_params(prog);
>
> prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
> - is_scalar_shader_stage(compiler, stage));
> + compiler->scalar_stage[stage]);
>
> _mesa_reference_program(ctx, &prog, NULL);
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
> index 1ccfa1b..2297fa6 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -126,6 +126,7 @@ brwProgramStringNotify(struct gl_context *ctx,
> struct gl_program *prog)
> {
> struct brw_context *brw = brw_context(ctx);
> + const struct brw_compiler *compiler = brw->intelScreen->compiler;
>
> switch (target) {
> case GL_FRAGMENT_PROGRAM_ARB: {
> @@ -165,7 +166,7 @@ brwProgramStringNotify(struct gl_context *ctx,
> brw_add_texrect_params(prog);
>
> prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_VERTEX,
> - brw->intelScreen->compiler->scalar_vs);
> + compiler->scalar_stage[MESA_SHADER_VERTEX]);
>
> brw_vs_precompile(ctx, NULL, prog);
> break;
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index 1cf00f4..04cd6a8 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -72,22 +72,6 @@ shader_perf_log_mesa(void *data, const char *fmt, ...)
> va_end(args);
> }
>
> -bool
> -is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
> -{
> - switch (stage) {
> - case MESA_SHADER_FRAGMENT:
> - case MESA_SHADER_COMPUTE:
> - return true;
> - case MESA_SHADER_GEOMETRY:
> - return compiler->scalar_gs;
> - case MESA_SHADER_VERTEX:
> - return compiler->scalar_vs;
> - default:
> - return false;
> - }
> -}
> -
> struct brw_compiler *
> brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
> {
> @@ -100,11 +84,12 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
> brw_fs_alloc_reg_sets(compiler);
> brw_vec4_alloc_reg_set(compiler);
>
> - if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
> - compiler->scalar_vs = true;
> -
> - if (devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
> - compiler->scalar_gs = true;
> + compiler->scalar_stage[MESA_SHADER_VERTEX] =
> + devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
> + compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
> + devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false);
> + compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
> + compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
>
> nir_shader_compiler_options *nir_options =
> rzalloc(compiler, nir_shader_compiler_options);
> @@ -137,7 +122,7 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
> compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
> compiler->glsl_compiler_options[i].LowerClipDistance = true;
>
> - bool is_scalar = is_scalar_shader_stage(compiler, i);
> + bool is_scalar = compiler->scalar_stage[i];
>
> compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
> compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
> @@ -152,7 +137,7 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
> compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
> }
>
> - if (compiler->scalar_gs)
> + if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
> compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
>
> return compiler;
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
> index 29baebf..7cca201 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.h
> +++ b/src/mesa/drivers/dri/i965/brw_shader.h
> @@ -279,8 +279,6 @@ int type_size_scalar(const struct glsl_type *type);
> int type_size_vec4(const struct glsl_type *type);
> int type_size_vec4_times_4(const struct glsl_type *type);
>
> -bool is_scalar_shader_stage(const struct brw_compiler *compiler, int stage);
> -
> #ifdef __cplusplus
> }
> #endif
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index 5cba3b3..c5ffaf0 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -2055,7 +2055,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
> * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
> * vec4 mode, the hardware appears to wedge unless we read something.
> */
> - if (compiler->scalar_vs)
> + if (compiler->scalar_stage[MESA_SHADER_VERTEX])
> prog_data->base.urb_read_length = DIV_ROUND_UP(nr_attributes, 2);
> else
> prog_data->base.urb_read_length = DIV_ROUND_UP(MAX2(nr_attributes, 1), 2);
> @@ -2074,7 +2074,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
> else
> prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4);
>
> - if (compiler->scalar_vs) {
> + if (compiler->scalar_stage[MESA_SHADER_VERTEX]) {
> prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
>
> fs_visitor v(compiler, log_data, mem_ctx, key, &prog_data->base.base,
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> index 1a09f76..81353ae 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
> @@ -819,7 +819,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
> brw_print_vue_map(stderr, &prog_data->base.vue_map);
> }
>
> - if (compiler->scalar_gs) {
> + if (compiler->scalar_stage[MESA_SHADER_GEOMETRY]) {
> /* TODO: Support instanced GS. We have basically no tests... */
> assert(prog_data->invocations == 1);
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
> index 967448e..7c783f6 100644
> --- a/src/mesa/drivers/dri/i965/brw_vs.c
> +++ b/src/mesa/drivers/dri/i965/brw_vs.c
> @@ -48,6 +48,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
> struct brw_vertex_program *vp,
> struct brw_vs_prog_key *key)
> {
> + const struct brw_compiler *compiler = brw->intelScreen->compiler;
> GLuint program_size;
> const GLuint *program;
> struct brw_vs_prog_data prog_data;
> @@ -79,7 +80,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
> * by the state cache.
> */
> int param_count = vp->program.Base.nir->num_uniforms;
> - if (!brw->intelScreen->compiler->scalar_vs)
> + if (!compiler->scalar_stage[MESA_SHADER_VERTEX])
> param_count *= 4;
>
> if (vs)
> @@ -102,7 +103,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
> if (prog) {
> brw_nir_setup_glsl_uniforms(vp->program.Base.nir, prog, &vp->program.Base,
> &prog_data.base.base,
> - brw->intelScreen->compiler->scalar_vs);
> + compiler->scalar_stage[MESA_SHADER_VERTEX]);
> } else {
> brw_nir_setup_arb_uniforms(vp->program.Base.nir, &vp->program.Base,
> &prog_data.base.base);
> @@ -173,7 +174,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
> /* Emit GEN4 code.
> */
> char *error_str;
> - program = brw_compile_vs(brw->intelScreen->compiler, brw, mem_ctx, key,
> + program = brw_compile_vs(compiler, brw, mem_ctx, key,
> &prog_data, vp->program.Base.nir,
> brw_select_clip_planes(&brw->ctx),
> !_mesa_is_gles3(&brw->ctx),
> --
> 2.6.2
>
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