[Mesa-dev] [PATCH] [v3] i965/skl: skip fast clears for certain surface formats

[Chad Versace]

On Wed 18 Nov 2015, Pohjolainen, Topi wrote:
> On Tue, Nov 17, 2015 at 05:31:12PM -0800, Ben Widawsky wrote:
> > Some of the information originally in this commit message is now in the patch
> > before this.
> >
> > SKL adds compressible render targets and as a result mutates some of the
> > programming for fast clears and resolves. There is a new internal surface type
> > called the CCS. The old AUX_MCS bit becomes AUX_CCS_D. "The Auxiliary surface is
> > a CCS (Color Control Surface) with compression disabled or an MCS with
> > compression enabled, depending on number of multisamples. MCS (Multisample
>
> I find this wording (even though it looks to be directly from the spec
> somewhat misleading. I read it suggesting that AUX can be CCS only when
> compression is disabled. I like another wording in "Auxiliary Surfaces For
> Sampled Tiled Resource" better: "CCS is used to indicate that the color
> surface is losslessly compressed."

The BSpec docs regarding CCS are universally confusing.

To clarify the subject, here is a summary how the BSpec usage of the
terms "MCS" and "CCS" differ between BDW and SKL.

    BDW > RENDER_SURFACE_STATE > Auxiliary Surface Mode:

        AUX_MCS, if samples > 1:

            The aux surface is a "Multisample Control Surface".

            Let N be the surfaces's sample count.  Each element of the MCS is
            a packed array of N subelements, one subelement per sample. Each
            subelement contains log2(N) bits, and therefore has the range [0,
            N-1]. The total element size is byte-aligned. See the PRM section
            titled "Compressed Multisampled Surfaces" for the full details of
            the bit layout.

            For each sample (x, y, s) of the "logical" surface, the MCS element
            at location (x, y) defines which array slice of the primary surface
            contains the color value for sample s. For example, if N=4 and the
            MCS element at some pixel location (x0, y0) is 11010000b, then it
            defines the mapping:
                (x0, y0, 0) => array slice 0
                (x0, y0, 1) => array slice 0
                (x0, y0, 2) => array slice 1
                (x0, y0, 3) => array slice 3

            A special case occurs if the MCS element at some location (x0, y0)
            indicates that the color value of all samples (x0, y0, s) of pixel
            (x0, y0) are stored in array slice N-1.  This special case occurs
            when all bits are set in the MCS element.  In this case, the pixel
            value stored at location (x0, y0) in each array slice of the primary
            surface is undefined. The pixel value for all samples is instead the
            surface's clear color, which is set in
            RENDER_SURFACE_STATE.*ClearColor.

        AUX_MCS, if samples == 1:
            The aux suface is a degenerate form of the "Multisample Control
            Surface".

            The PRM calls this degenerate form of the MCS the "non-MSRT MCS"
            (non-Mulisampled Render Target Multisample Control Surface). The
            name is horrifically contradictory.

            Each MCS element is 1 bit. The MCS is tightly packed (that is,
            1 byte contains 8 elements). Each MCS element contains the clear
            status of a cache line pair (128B) in the primary surface.  If the
            MCS element's bit is set, then all color values stored in the
            2 cache lines of the primary surface are invalid; the real color
            value, for all pixels in the cache line pair, is the clear color set
            in RENDER_SURFACE_STATE.*ClearColor.

    SKL > RENDER_SURFACE_STATE > Auxiliary Surface Mode:

        AUX_CCS_D, if samples > 1:
            The aux surface is a Multisample Control Surface. It's identical to
            the Broadwell MCS.

        AUX_CCS_E, if samples > 1:
            Same as AUX_CCS_D.  The aux surface is again a Multisample Control
            Surface, identical to the Broadwell MCS.

        AUX_CCS_D, if samples == 1:
            The aux surface is a "Color Control Surface" with compression "Disabled".

            Sometimes the BSpec refers to the compression as "Render
            Compression", "color compression", and "lossless color
            compression". I believe they all mean the same thing.

            Skylake's AUX_CCS_D surface has the same layout as
            Broadwell's non-MSRT MCS, except that each CCS element is
            2 bits instead of 1. In other words, each 2bit element in
            the CCS_D contains the clear status of a cache-line pair
            (128B) in the primary surface. If all bits in the CCS_D element
            is set, then all color values stored in the 2 cache lines of
            the primary surface are invalid; the real color value, for
            all pixels in the cache line pair, is the clear color set in
            RENDER_SURFACE_STATE.*ClearColor.

        AUX_CCS_E, if samples == 1:
            The aux surface is a "Color Control Surface" with
            compression "Enabled".

            Similar to the single-sampled CCS_D, each CCS_E element is
            2 bits and contains the compression status of a cache-line
            pair (128B) in the primary surface.

            The display engine somewhat understands CCS_E.
            (I don't fully understand that subject).

            I don't understand the details of the CCS_E compression
            format. Maybe you can research that and teach me?