[Mesa-dev] [PATCH 3/7] i965/vec4: Use a stride of 1 and byte offsets for UBOs

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp       | 16 +++-------------
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   | 13 +++----------
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  5 +----
 3 files changed, 7 insertions(+), 27 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 8453dc2..16d3a06 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -786,20 +786,10 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
       unsigned const_offset = instr->const_index[0];
       src_reg offset;
 
-      if (devinfo->gen <= 6) {
-         if (!has_indirect)  {
-            offset = brw_imm_ud(const_offset & ~15);
-         } else {
-            offset = get_nir_src(instr->src[1], nir_type_int, 1);
-         }
+      if (!has_indirect)  {
+         offset = brw_imm_ud(const_offset & ~15);
       } else {
-         if (!has_indirect)  {
-            offset = brw_imm_ud(const_offset / 16);
-         } else {
-            offset = src_reg(this, glsl_type::uint_type);
-            emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
-                     brw_imm_ud(4u)));
-         }
+         offset = get_nir_src(instr->src[1], nir_type_int, 1);
       }
 
       src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 71ec9da..51e6227 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1473,23 +1473,16 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
 
       emit_before(block, inst, ADD(dst_reg(index), *reladdr,
                                    brw_imm_d(reg_offset)));
-
-      /* Pre-gen7, the message header uses byte offsets instead of vec4
-       * (16-byte) offset units.
-       */
-      if (devinfo->gen < 7) {
-         emit_before(block, inst, MUL(dst_reg(index), index, brw_imm_d(16)));
-      }
+      emit_before(block, inst, MUL(dst_reg(index), index, brw_imm_d(16)));
 
       return index;
    } else if (devinfo->gen >= 8) {
       /* Store the offset in a GRF so we can send-from-GRF. */
       src_reg offset = src_reg(this, glsl_type::int_type);
-      emit_before(block, inst, MOV(dst_reg(offset), brw_imm_d(reg_offset)));
+      emit_before(block, inst, MOV(dst_reg(offset), brw_imm_d(reg_offset * 16)));
       return offset;
    } else {
-      int message_header_scale = devinfo->gen < 7 ? 16 : 1;
-      return brw_imm_d(reg_offset * message_header_scale);
+      return brw_imm_d(reg_offset * 16);
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 7cb7dd5..c016667 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -403,12 +403,9 @@ brw_create_constant_surface(struct brw_context *brw,
 			    uint32_t *out_offset,
                             bool dword_pitch)
 {
-   uint32_t stride = dword_pitch ? 1 : 16;
-   uint32_t elements = ALIGN(size, stride) / stride;
-
    brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
                                        BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
-                                       elements, stride, false);
+                                       size, 1, false);
 }
 
 /**
-- 
2.5.0.400.gff86faf