[Mesa-dev] [PATCH 2/2] r600: add missing register to initial state
Marek Olšák
maraeo at gmail.com
Tue Nov 24 02:28:46 PST 2015
For the series:
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Marek
On Mon, Nov 23, 2015 at 11:46 PM, Dave Airlie <airlied at gmail.com> wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists
> on all evergreen not just cayman, so we should initialise
> it as well.
>
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
> src/gallium/drivers/r600/evergreen_compute.c | 2 +-
> src/gallium/drivers/r600/evergreen_state.c | 19 ++++++++++++++-----
> src/gallium/drivers/r600/evergreend.h | 1 -
> 3 files changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
> index 5743e3f..010d109 100644
> --- a/src/gallium/drivers/r600/evergreen_compute.c
> +++ b/src/gallium/drivers/r600/evergreen_compute.c
> @@ -402,7 +402,7 @@ static void evergreen_emit_direct_dispatch(
> assert(lds_size <= 8160);
> }
>
> - radeon_compute_set_context_reg(cs, CM_R_0288E8_SQ_LDS_ALLOC,
> + radeon_compute_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC,
> lds_size | (num_waves << 14));
>
> /* Dispatch packet */
> diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
> index 684eee7..5333761 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -2266,7 +2266,7 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
> struct r600_command_buffer *cb = &rctx->start_cs_cmd;
> int tmp, i;
>
> - r600_init_command_buffer(cb, 320);
> + r600_init_command_buffer(cb, 326);
>
> /* This must be first. */
> r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
> @@ -2324,8 +2324,8 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
> r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
> r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
>
> - r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
> - r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
> + r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
> + r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
> r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
>
> r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
> @@ -2375,6 +2375,9 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
> r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> + r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> + r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> +
> r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
>
> /* to avoid GPU doing any preloading of constant from random address */
> @@ -2545,7 +2548,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
> return;
> }
>
> - r600_init_command_buffer(cb, 320);
> + r600_init_command_buffer(cb, 330);
>
> /* This must be first. */
> r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
> @@ -2817,6 +2820,8 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
> r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
> + r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
> + r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
>
> /* to avoid GPU doing any preloading of constant from random address */
> r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
> @@ -2851,7 +2856,11 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
> r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
> r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
> r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
> - r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0);
> +
> + r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
> + r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
> + r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
> +
> r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0);
>
> eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
> diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
> index dbee9d5..c43a987 100644
> --- a/src/gallium/drivers/r600/evergreend.h
> +++ b/src/gallium/drivers/r600/evergreend.h
> @@ -2500,7 +2500,6 @@
> #define CM_R_0286FC_SPI_LDS_MGMT 0x286fc
> #define S_0286FC_NUM_PS_LDS(x) ((x) & 0xff)
> #define S_0286FC_NUM_LS_LDS(x) ((x) & 0xff) << 8
> -#define CM_R_0288E8_SQ_LDS_ALLOC 0x000288E8
>
> #define CM_R_028804_DB_EQAA 0x00028804
> #define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0)
> --
> 2.4.3
>
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