[Mesa-dev] [PATCH 06/20] i965: Assign hw-binding table index for each UBO constant buffer.

Abdiel Janulgue abdiel.janulgue at linux.intel.com
Fri Sep 11 01:33:20 PDT 2015


To be able to refer to a constant buffer, the resource streamer needs
to index it with a hardware binding table entry. This blankets the ubo
buffers with hardware binding table indices.

Gather constants hardware fetches in 16-entry binding table blocks.
So we need to use a block that is unused.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h          | 11 +++++++++++
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  6 ++++++
 2 files changed, 17 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index de0db5a..58edaf4 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -762,6 +762,17 @@ struct brw_vs_prog_data {
 
 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
 
+/** Start of hardware binding table index for uniform gather constant entries.
+ *  This must be aligned to the start of a hardware binding table block (a block
+ *  is a group 16 binding table entries).
+ */
+#define BRW_UNIFORM_GATHER_INDEX_START 32
+
+/** Appended to the end of the binding table index for uniform constant buffers
+ *  to indicate start of the UBO gather constant binding table.
+ */
+#define BRW_UBO_GATHER_INDEX_APPEND 2
+
 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
  * this struct!
  */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8213f4e..fab553b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -917,6 +917,12 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
                                   bo->size - binding->Offset,
                                   &surf_offsets[i],
                                   dword_pitch);
+      if (brw->gather_pool.bo) {
+         int bt_idx = BRW_UNIFORM_GATHER_INDEX_START +
+            BRW_UBO_GATHER_INDEX_APPEND + i;
+         gen7_edit_hw_binding_table_entry(brw, stage_state->stage,
+                                          bt_idx, surf_offsets[i]);
+      }
    }
 
    if (shader->NumUniformBlocks)
-- 
1.9.1



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