[Mesa-dev] [PATCH] gallium/ttn: add LODQ support

[Ilia Mirkin]

Hm, just realized this messes up for shadow textures. Oh well, this
can wait until there's an actual impl on the other end.

On Sun, Sep 13, 2015 at 12:28 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
>
> I was going to add freedreno support for this, but... I couldn't figure
> out how to get the GETLOD opcode to return the results I wanted. Figured
> I'd send this out thought.
>
>  src/gallium/auxiliary/nir/tgsi_to_nir.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
> index cccc560..9aa6edd 100644
> --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
> +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
> @@ -1122,6 +1122,10 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
>        num_srcs = 3;
>        samp = 3;
>        break;
> +   case TGSI_OPCODE_LODQ:
> +      op = nir_texop_lod;
> +      num_srcs = 1;
> +      break;
>
>     default:
>        fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
> @@ -1488,7 +1492,7 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
>     [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
>
>     [TGSI_OPCODE_TG4] = 0,
> -   [TGSI_OPCODE_LODQ] = 0, /* XXX */
> +   [TGSI_OPCODE_LODQ] = 0,
>
>     [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
>     [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
> @@ -1655,6 +1659,7 @@ ttn_emit_instruction(struct ttn_compile *c)
>     case TGSI_OPCODE_TXQ_LZ:
>     case TGSI_OPCODE_TXF:
>     case TGSI_OPCODE_TG4:
> +   case TGSI_OPCODE_LODQ:
>        ttn_tex(c, dest, src);
>        break;
>
> --
> 2.4.6
>