[Mesa-dev] [PATCH v5 02/70] i965: Use 16-byte offset alignment for shader storage buffers

[Kristian Høgsberg]

On Thu, Sep 10, 2015 at 03:35:18PM +0200, Iago Toral Quiroga wrote:
> This is the same we do for other things like uniforms because it ensures
> optimal performance.
> 
> Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 907b2a0..c8e8a68 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -558,6 +558,7 @@ brw_initialize_context_constants(struct brw_context *brw)
>      * However, unaligned accesses are slower, so enforce buffer alignment.
>      */
>     ctx->Const.UniformBufferOffsetAlignment = 16;
> +   ctx->Const.ShaderStorageBufferOffsetAlignment = 16;

This should be a cacheline (64 bytes) so that we can safely have the
CPU and GPU writing the same SSBO on non-cachecoherent systems (our
Atom CPUs).  With UBOs, the GPU never writes, so there's no
problem. For an SSBO, the GPU and the CPU can be updating disjoint
regions of the buffer simultaneously and that will break if the
regions overlap the same cacheline.

With that change,

Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>

>     ctx->Const.TextureBufferOffsetAlignment = 16;
>     ctx->Const.MaxTextureBufferSize = 128 * 1024 * 1024;
>  
> -- 
> 1.9.1
>