[Mesa-dev] [PATCH] i965/vec4: Don't coalesce registers in gen6 math ops if reswizzling needed

[Kenneth Graunke]

On Sunday, September 20, 2015 11:11:15 AM Matt Turner wrote:
> On Sun, Sep 20, 2015 at 8:48 AM, Antia Puentes <apuentes at igalia.com> wrote:
> > Math operations in SandyBridge do not support source swizzling
> 
> I can't find any documentation to support this claim, but I remember
> that SNB math must be in align1 mode so it can't do swizzles or
> writemasking (see commit e14cc504).
> 
> But, the documentation actually says "The supported regioning modes
> for math instruction are align16, align1 with the following
> restrictions: ..."
> 
> Would be nice if we could actually find a PRM citation.

I can't find a PRM citation that mentions swizzles explicitly.  However,
the "Src Mod" box is unchecked, indicating that the MATH instruction
can't handle source modifiers.  vec4_visitor::fix_math_operand's
comments interpret that as abs, negate, /and/ swizzles.  Which sort of
makes sense.

In the internal docs, I see [reformatting mine]:

"[DevSNB], [DevIVB], [DevHSW]:
 The supported regioning mode for math instruction is align1 with
 the following restrictions:

 * Scalar source is supported.
 * Source and destination horizontal stride must be 1.
 * Width must be the same as execution size.
 * Source and destination offset must be the same, except the case
 * of scalar source.
 * The math instruction does not support indirect addressing modes"

(Those comments are also in the Haswell PRM.)

vs.

"[DevBDW]:
 The supported regioning mode for math instruction is align1 and
 align16.  The following restrictions apply for align1 mode:

 * Scalar source is supported.
 * Source and destination horizontal stride must be the same.
 * Regioning must ensure Src.Vstride = Src.Width * Src.Hstride
 * Source and destination offset must be the same, except the case of
   scalar source."

Unfortunately, I couldn't find the above "it must be align1" comments
in any of the PRMs until Haswell.  I assume it just got lost.
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